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1. 发明申请

WO2008135554A1 METHOD FOR FORMING A PLANAR STACKED GATE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING GATE ELECTRODE AND DEVICES OBTAINED THEREOF 审中-公开
标题翻译：用于形成具有浮动栅电极的平面堆叠栅非易失性半导体存储器件的方法及其获得的器件
公开(公告)号：WO2008135554A1
公开(公告)日：2008-11-13
申请号：PCT/EP2008/055493
申请日：2008-05-05
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , DE VOS, Joeri , HASPESLAGH, Luc
发明人： DE VOS, Joeri , HASPESLAGH, Luc
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： A method of fabricating a stacked gate nonvolatile memory device, comprising the steps of forming a plurality of conductive floating gate structures above channel regions of the substrate, isolated from each other by a dielectric, the floating gate structure shaving a larger coupling ratio with control gates than with channel regions in the substrate. This comprises the steps of: (a) first forming the dielectric with cavities exposing the substrate at the channel regions, the cavities having predetermined shapes for shaping thefloating gate structures such that their top sides have a larger area than their bottom sides, and (b) afterwards forming the floating gate structures in the cavities. A stacked gate nonvolatile memory device, comprising: a semiconductor substrate; a dielectric formed on the semiconductor substrate, the dielectric comprising cavities exposing the semiconductor substrate at channel regions; and homogenous floating gate structures in the cavities having a larger coupling ratio with thecontrol gates than with channel regions in the substrate.
摘要翻译：一种制造堆叠栅极非易失性存储器件的方法，包括以下步骤：通过电介质彼此隔离的在衬底的通道区域上方形成多个导电浮栅结构，浮栅结构与控制栅极剃须更大的耦合比比衬底中的沟道区域。这包括以下步骤：（a）首先形成具有在沟道区域暴露衬底的空腔的电介质，空腔具有用于使浮选栅极结构成形的预定形状，使得其顶侧具有比其底侧更大的面积，以及（b ）之后在空腔中形成浮栅结构。一种堆叠栅极非易失性存储器件，包括：半导体衬底; 形成在所述半导体衬底上的电介质，所述电介质包括在沟道区域暴露所述半导体衬底的空腔; 并且在腔中具有与控制栅极的耦合比率大于衬底中的沟道区域的均匀浮栅结构。

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