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    • 7. 发明申请
    • LO GENERATION WITH DESKEWED INPUT OSCILLATOR SIGNAL AND SINGLE ENDED DYNAMIC DIVIDER FOR DIFFERENTIAL QUADRATURE SIGNALS
    • 具有输入振荡器信号和单端动态分频器的LO生成用于差分三角形信号
    • WO2010057037A3
    • 2011-04-28
    • PCT/US2009064456
    • 2009-11-13
    • QUALCOMM INCPANIKKATH VINOD VGUDEM PRASAD SCICCARELLI STEVEN C
    • PANIKKATH VINOD VGUDEM PRASAD SCICCARELLI STEVEN C
    • H03B19/12H03D7/16
    • H03B19/12G01R13/02H03B27/00H03D7/16
    • Techniques for generating local oscillator (LO) signals are described. In one design, an apparatus may include a deskew circuit and a divider circuit. The deskew circuit may receive a differential input oscillator signal having timing skew and provide a differential output oscillator signal having reduced timing skew. The differential input oscillator signal may include first and second input oscillator signals, and the differential output oscillator signal may include first and second output oscillator signals. In one design, the deskew circuit may include first and second variable delay circuits that receive the first and second input oscillator signals, respectively, and provide the first and second output oscillator signals, respectively. Each output oscillator signal may have an adjustable delay selected to reduce timing skew. The divider circuit may divide the differential output oscillator signal in frequency and provide differential I and Q divided signals, which may be used to generate LO signals.
    • 描述用于产生本地振荡器(LO)信号的技术。 在一种设计中,设备可以包括去歪斜电路和分频器电路。 偏移电路可以接收具有定时偏移的差分输入振荡器信号,并提供具有减小的定时偏移的差分输出振荡器信号。 差分输入振荡器信号可以包括第一和第二输入振荡器信号,并且差分输出振荡器信号可以包括第一和第二输出振荡器信号。 在一种设计中,歪斜电路可以包括分别接收第一和第二输入振荡器信号的第一和第二可变延迟电路,并分别提供第一和第二输出振荡器信号。 每个输出振荡器信号可以具有选择的可调延迟以减少定时偏移。 分频器电路可以分频差分输出振荡器信号,并提供差分I和Q分频信号,可用于产生LO信号。
    • 8. 发明申请
    • LO GENERATION WITH DESKEWED INPUT OSCILLATOR SIGNAL
    • LO生成与输入振荡器信号
    • WO2010057037A2
    • 2010-05-20
    • PCT/US2009/064456
    • 2009-11-13
    • QUALCOMM INCORPORATEDPANIKKATH, Vinod, V.GUDEM, Prasad, S.CICCARELLI, Steven, C.
    • PANIKKATH, Vinod, V.GUDEM, Prasad, S.CICCARELLI, Steven, C.
    • H03B19/00
    • H03B19/12G01R13/02H03B27/00H03D7/16
    • Techniques for generating local oscillator (LO) signals are described. In one design, an apparatus may include a deskew circuit and a divider circuit. The deskew circuit may receive a differential input oscillator signal having timing skew and provide a differential output oscillator signal having reduced timing skew. The differential input oscillator signal may include first and second input oscillator signals, and the differential output oscillator signal may include first and second output oscillator signals. In one design, the deskew circuit may include first and second variable delay circuits that receive the first and second input oscillator signals, respectively, and provide the first and second output oscillator signals, respectively. Each output oscillator signal may have an adjustable delay selected to reduce timing skew. The divider circuit may divide the differential output oscillator signal in frequency and provide differential I and Q divided signals, which may be used to generate LO signals.
    • 描述用于产生本地振荡器(LO)信号的技术。 在一种设计中,设备可以包括去歪斜电路和分频器电路。 偏移电路可以接收具有定时偏移的差分输入振荡器信号,并提供具有减小的定时偏移的差分输出振荡器信号。 差分输入振荡器信号可以包括第一和第二输入振荡器信号,并且差分输出振荡器信号可以包括第一和第二输出振荡器信号。 在一种设计中,歪斜电路可以包括分别接收第一和第二输入振荡器信号的第一和第二可变延迟电路,并分别提供第一和第二输出振荡器信号。 每个输出振荡器信号可以具有选择的可调延迟以减少定时偏移。 分频器电路可以分频差分输出振荡器信号,并提供差分I和Q分频信号,可用于产生LO信号。
    • 10. 发明申请
    • DYNAMIC REFERENCE FREQUENCY FOR FRACTIONAL-N PHASE-LOCKED LOOP
    • 分段N相锁定环路的动态参考频率
    • WO2009111346A1
    • 2009-09-11
    • PCT/US2009/035577
    • 2009-02-27
    • QUALCOMM IncorporatedCICCARELLI, Steven C.BOSSU, FredericAPARIN, VladimirWANG, Kevin H.
    • CICCARELLI, Steven C.BOSSU, FredericAPARIN, VladimirWANG, Kevin H.
    • H03L7/197H04B15/06
    • H03L7/1974
    • Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.
    • 在接收机内,提供给分数N锁相环(PLL)的比较参考时钟信号的频率被动态地改变,使得具有已知干扰的参考杂波(例如,传输泄漏)的不期望的相互混合被最小化。 当发射信道在频带内变化时,并且随着发射泄漏频率的变化,电路改变比较参考时钟信号的频率,使得PLL产生的参考杂波频率移动,使得它们不与发射机泄漏相互混合 以不良的方式。 在第二方面,PLL可以作为整数N个PLL或分数N PLL来操作。 在低总接收功率情况下,PLL作为整数N PLL进行操作,以减少接收机对分数N个杂散的敏感性。 在第三方面,使用干扰检测信息来确定比较参考时钟信号频率。