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1. 发明申请

WO2009151894A1 NONVOLATILE MEMORY AND METHOD WITH INDEX PROGRAMMING AND REDUCED VERIFY 审中-公开
标题翻译：非易失性存储器和方法与索引编程和减少的验证
公开(公告)号：WO2009151894A1
公开(公告)日：2009-12-17
申请号：PCT/US2009/044554
申请日：2009-05-19
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian
发明人： CERNEA, Raul-Adrian
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.
摘要翻译：在非易失性存储器中，使用多通道索引编程方法将一组存储器单元分别编程到其目标状态，这减少了验证步骤的数量。对于每个单元，程序索引保持存储施加到单元的最后编程电压。在第一次编程过程中，每个单元都应用一系列增量编程脉冲进行索引。第一个编程通过之后是验证和一个或多个后续编程传递，以修剪对各个目标状态的任何短暂的下降。如果单元无法验证到其目标状态，则其程序索引增加，并允许通过来自最后接收的脉冲的下一个脉冲对单元进行编程。重复验证和编程遍历，直到组中的所有单元格被验证到其各自的目标状态。不需要脉冲之间的验证操作。

2. 发明申请

WO2008124760A3 NON-VOLATILE MEMORY AND METHOD FOR PREDICTIVE PROGRAMMING 审中-公开
标题翻译：非易失性存储器和预测编程方法
公开(公告)号：WO2008124760A3
公开(公告)日：2008-11-27
申请号：PCT/US2008059740
申请日：2008-04-09
申请人： SANDISK CORP , CERNEA RAUL-ADRIAN
发明人： CERNEA RAUL-ADRIAN
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. The checkpoint is an actual programming voltage that programs the memory cell in question to a verified designated threshold voltage level.
摘要翻译：在具有存储器单元阵列的非易失性存储器中，其中存储器单元可个别地编程到阈值电压电平范围中的一个，提供了预测编程模式，其中预定函数预测编程电压电平需要施加在为了将给定的存储器单元编程到给定的目标阈值电压电平。这样就不需要执行验证操作，从而大大提高了编程操作的性能。在一个优选实施例中，预定函数是线性的并且在编程时通过一个或多个检查点针对每个存储器单元进行校准。检查点是一个实际的编程电压，用于将所讨论的存储单元编程为经验证的指定阈值电压电平。

3. 发明申请

WO2007001911A1 COMPENSATION CURRENTS IN NON-VOLATILE MEMORY READ OPERATIONS 审中-公开
标题翻译：非易失性存储器读取操作中的补偿电流
公开(公告)号：WO2007001911A1
公开(公告)日：2007-01-04
申请号：PCT/US2006/023541
申请日：2006-06-15
申请人： SANDISK CORPORATION , CERNEA, Raul-adrian
发明人： CERNEA, Raul-adrian
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C7/02 , G11C7/12 , G11C16/26
摘要： Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and consequently, lowering the sensed conduction current of a memory cell. The read process for a selected memory cell takes into account the state of one or more adjacent memory cells. If an adjacent memory cell is in one or more of a predetermined set of programmed states, a compensation current can be provided to increase the apparent conduction current of the selected memory cell. An initialization voltage is provided to the bit line of the programmed adjacent memory cell to induce a compensation current between the bit line of the programmed adjacent memory cell and the bit line of the selected memory cell.
摘要翻译：存储在非易失性存储单元的浮动栅极上的视在电荷的变化可能由于基于存储在相邻浮动栅极中的电荷的电场的耦合而发生。表观电荷的偏移可能导致误差读数，因为提高了视在阈值电压，从而降低了感测的存储单元的传导电流。所选择的存储器单元的读取处理考虑了一个或多个相邻存储器单元的状态。如果相邻存储器单元处于预定的一组编程状态中的一个或多个，则可以提供补偿电流以增加所选存储单元的表观传导电流。将初始化电压提供给编程的相邻存储器单元的位线，以在编程的相邻存储单元的位线和所选存储单元的位线之间产生补偿电流。

4. 发明申请

WO2005066975A1 FLEXIBLE AND AREA EFFICIENT COLUMN REDUNDANCY FOR NON-VOLATILE MEMORIES 审中-公开
标题翻译：灵活和有效的色谱柱冗余非挥发性记忆
公开(公告)号：WO2005066975A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/042990
申请日：2004-12-20
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian , LI, Yan
发明人： CERNEA, Raul-Adrian , LI, Yan
IPC分类号： G11C29/00
CPC分类号： G11C7/1036 , G11C29/848
摘要： The present invention presents a non-volatile memory wherein bad columns in the array of memory cells can be removed. According to another aspect of the present invention, substitute redundant columns can replace the removed columns. Both of these processes are performed on the memory in a manner that is externally transparent and, consequently, need not be managed externally by the host or controller to which the memory is attached. An inventory of the bad columns can be maintained on the memory. At power up, the list of bad columns is used to fuse out the bad columns. The memory may also contain a number of redundant columns that can be used to replace the bad columns.
摘要翻译：本发明提供了一种非易失性存储器，其中可以去除存储器单元阵列中的不良列。根据本发明的另一方面，替代冗余列可以替代所移除的列。这些处理都以外部透明的方式在存储器上执行，因此不需要由附加存储器的主机或控制器在外部进行管理。可以在内存上维护坏列的清单。上电时，不良列的列表用于对不良列进行融合。内存还可能包含一些可用于替换不良列的冗余列。

5. 发明申请

WO2003025937A3 BACKGROUND OPERATION FOR MEMORY CELLS 审中-公开
公开(公告)号：WO2003025937A3
公开(公告)日：2003-03-27
申请号：PCT/US2002/029554
申请日：2002-09-17
申请人： SANDISK CORPORATION , CERNEA, Raul, Adrian
发明人： CERNEA, Raul, Adrian
IPC分类号： G11C16/16
摘要： A technique to perform an operation (e.g., erase, program, or read) on memory cells (105) is to apply an operating voltage dynamically to the gates (111, 113) of the memory cells, rather than a continuous operating voltage. This reduces the power consumed during the operation. Dynamic operation or background operation such as background erase also permits other operations, such as read, program, or erase, to occur while the selected memory cells are operated on. This improves the operational speed of an integrated circuit using dynamic operation compared to a continuous operation. In an embodiment for background erase, the erase gates are charged to the erase voltage using a charge pump (204, 208). The pump is then turned off (212), and the erase gates remain at the erase voltage dynamically (216). The erase voltage at the erase gates will be periodically checked and refreshed as needed until the memory cells are fully erased (224). While the charge pump is off and the erase voltage is dynamically held at the erase dates, other operations, possibly on other memory cells, may be performed (220).

6. 发明申请

WO03025937A2 BACKGROUND OPERATION FOR MEMORY CELLS 审中-公开
标题翻译：存储器单元的背景操作
公开(公告)号：WO03025937A2
公开(公告)日：2003-03-27
申请号：PCT/US0229554
申请日：2002-09-17
申请人： SANDISK CORP , CERNEA RAUL ADRIAN
发明人： CERNEA RAUL ADRIAN
IPC分类号： G11C16/06 , G11C8/08 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/12 , G11C16/30 , G11C
CPC分类号： G11C16/0483 , G11C8/08 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C2216/18
摘要： A technique to perform an operation (e.g., erase, program, or read) on memory cells (105) is to apply an operating voltage dynamically to the gates (111, 113) of the memory cells, rather than a continuous operating voltage. This reduces the power consumed during the operation. Dynamic operation or background operation such as background erase also permits other operations, such as read, program, or erase, to occur while the selected memory cells are operated on. This improves the operational speed of an integrated circuit using dynamic operation compared to a continuous operation. In an embodiment for background erase, the erase gates are charged to the erase voltage using a charge pump (204, 208). The pump is then turned off (212), and the erase gates remain at the erase voltage dynamically (216). The erase voltage at the erase gates will be periodically checked and refreshed as needed until the memory cells are fully erased (224). While the charge pump is off and the erase voltage is dynamically held at the erase dates, other operations, possibly on other memory cells, may be performed (220).
摘要翻译：对存储器单元（105）执行操作（例如，擦除，编程或读取）的技术是将动态电压动态地施加到存储器单元的栅极（111,113），而不是连续的操作电压。这减少了操作过程中的功耗。动态操作或背景操作（如后台擦除）还允许在选定的存储单元操作时发生其他操作，例如读取，编程或擦除。与连续操作相比，这提高了使用动态操作的集成电路的操作速度。在用于背景擦除的实施例中，使用电荷泵（204,208）将擦除栅极充电到擦除电压。然后关闭泵（212），并且擦除栅极动态地保持在擦除电压（216）。擦除门处的擦除电压将根据需要被周期性地检查和刷新，直到存储单元被完全擦除（224）。当电荷泵关闭并且擦除电压动态保持在擦除日期时，可以执行其他操作（可能在其他存储器单元上）（220）。

7. 发明申请

WO2008083136A3 RESISTANCE SENSING AND COMPENSATION FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：电阻感测和补偿非易失性存储
公开(公告)号：WO2008083136A3
公开(公告)日：2008-12-11
申请号：PCT/US2007088786
申请日：2007-12-24
申请人： SANDISK CORP , MOKHLESI NIMA , CERNEA RAUL-ADRIAN
发明人： MOKHLESI NIMA , CERNEA RAUL-ADRIAN
IPC分类号： G11C16/26
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/26
摘要： When reading data from a non-volatile storage element that is part of a group of connected non-volatile storage elements, resistance information is measured for the group. One or more read parameters are set based on the measured resistance information. The read process is then performed using the one or more parameters.
摘要翻译：当从作为一组连接的非易失性存储元件的一部分的非易失性存储元件读取数据时，测量该组的电阻信息。基于所测量的电阻信息设置一个或多个读取参数。然后使用一个或多个参数执行读取过程。

8. 发明申请

WO2007112201A9 NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN DATA LATCHES FOR DEFECTIVE LOCATIONS 审中-公开
公开(公告)号：WO2007112201A9
公开(公告)日：2008-11-06
申请号：PCT/US2007063863
申请日：2007-03-13
申请人： SANDISK CORP , MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
发明人： MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
IPC分类号： G11C29/00 , G11C16/26
CPC分类号： G11C7/1063 , G11C7/1039 , G11C7/1051 , G11C16/04 , G11C16/10 , G11C29/846
摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

9. 发明申请

WO2007076414A3 REFERENCE SENSE AMPLIFIER AND METHOD FOR COMPENSATED SENSING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：参考信号放大器和非易失性存储器中的补偿感测方法
公开(公告)号：WO2007076414A3
公开(公告)日：2007-09-27
申请号：PCT/US2006062429
申请日：2006-12-20
申请人： SANDISK CORP , CHAN SIU LUNG , CERNEA RAUL-ADRIAN
发明人： CHAN SIU LUNG , CERNEA RAUL-ADRIAN
IPC分类号： G11C11/56 , G11C7/06 , G11C16/26
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/14 , G11C16/26 , G11C16/32 , G11C2207/063
摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
摘要翻译：用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。

10. 发明申请

WO2006065501A1 MEMORY SENSING CIRCUIT AND METHOD FOR LOW VOLTAGE OPERATION 审中-公开
标题翻译：存储感测电路和低电压运行方法
公开(公告)号：WO2006065501A1
公开(公告)日：2006-06-22
申请号：PCT/US2005/042854
申请日：2005-11-28
申请人： SANDISK CORPORATION , CERNEA, Raul-adrian
发明人： CERNEA, Raul-adrian
IPC分类号： G11C7/06 , G11C16/26 , G11C11/56
CPC分类号： G11C11/5642 , G11C7/062 , G11C7/067 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2207/063 , G11C2211/5621 , G11C2216/14 , G11C2216/22
摘要： A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line coupling. The rate of discharge of a dedicated capacitor as measured by a change in the voltage drop thereacross in a predetermined period is used to indicate the magnitude of the conduction current. The voltage cannot drop below a minimum level imposed by a circuit for maintaining the constant voltage condition on the bit line. A voltage shifter is used to boost the voltage during the discharge and to unboost the voltage after the discharge, so that the change in voltage drop properly reflects the rate of discharge without running into the minimum level.
摘要翻译：感测模块通过在恒定电压条件下经由耦合位线检测存储器单元的传导电流的读出放大器工作，以使位线到位线耦合最小化。通过在预定时间段内的电压降的变化来测量专用电容器的放电率，用于表示导通电流的大小。电压不能下降到电路所施加的最小电平以保持位线上的恒定电压状态。电压移位器用于在放电期间升高电压并且在放电之后解除电压，使得电压降的变化适当地反映放电速率而不会达到最小水平。

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