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1. 发明申请

WO2013154448A1 METHOD AND SYSTEM FOR AUTOMATICALLY ESTABLISHING A HIERARCHICAL PARAMETERIZED CELL (PCELL) DEBUGGING ENVIRONMENT 审中-公开
标题翻译：自动建立分层参数化细胞（PCELL）调试环境的方法和系统
公开(公告)号：WO2013154448A1
公开(公告)日：2013-10-17
申请号：PCT/RU2012/000273
申请日：2012-04-10
申请人： CADENCE DESIGN SYSTEMS, INC. , TING, Li-Chien , ANUFRIEV, Nikolay Vladimirovich , PESKOV, Alexey Nikolayevich , CALUYA, Serena Chiang , CHEN, Chia-Fu
发明人： TING, Li-Chien , ANUFRIEV, Nikolay Vladimirovich , PESKOV, Alexey Nikolayevich , CALUYA, Serena Chiang , CHEN, Chia-Fu
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F19/00 , G06F17/5081
摘要： A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow for the debugging of parameterized cells (PCELLS/PyCELLS) in a layout. A user may merely select a particular PCELL within a hierarchical PCELL and the system and method will determine dependencies thereof. The source code for the selected PCELL and its dependencies may be located and loaded. At least one breakpoint may be set in the source code of the selected PCELL. The source code for the selected PCELL and its dependencies may be executed to be arrested at the set breakpoints. Upon the arrest of execution, a debugging environment may be established and the located source code of the selected PCELL may be displayed along with values for parametric components thereof and progression control tools.
摘要翻译：提供了一种用于在电子设计自动化（EDA）工作流程中建立自动调试环境的系统和方法，用于在布局中调试参数化单元（PCELLS / PyCELLS）。用户可以仅选择分级PCELL内的特定PCELL，并且系统和方法将确定其依赖性。所选PCELL及其依赖项的源代码可能位于并加载。在所选择的PCELL的源代码中至少可以设置一个断点。所选PCELL的源代码及其依赖关系可能被执行为在设定的断点处被捕获。在执行停止之后，可以建立调试环境，并且所选择的PCELL的定位源代码可以与其参数分量和进程控制工具的值一起显示。

2. 发明申请

WO2009070177A1 SYSTEM AND METHOD FOR GENERATING FLAT LAYOUT 审中-公开
标题翻译：用于生成平面布局的系统和方法
公开(公告)号：WO2009070177A1
公开(公告)日：2009-06-04
申请号：PCT/US2007/086181
申请日：2007-11-30
申请人： CADENCE DESIGN SYSTEMS, INC. , GINETTI, Arnold
发明人： GINETTI, Arnold
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The present invention provides a method for generating flat layout design view that comprises importing port definitions of a first hierarchical block of digital instances from a source as a schematic symbol, importing port definitions of digital instances within the first hierarchical block from the source, instantiating the schematic symbol as a hierarchical layout instance in the flat layout, binding the hierarchical layout instance to the schematic symbol, and embedding digital layout block instances within the design layout by replacing the digital instances of a digital layout block with digital layout instances of a top layout module of the design layout.
摘要翻译：本发明提供了一种生成平面布局设计视图的方法，其包括将来自源的第一层数字实例的端口定义作为示意符号导入，从源中导入第一分层块内的数字实例的端口定义，原理图符号作为平面布局中的分层布局实例，将分层布局实例绑定到原理图符号，并将数字布局块实例嵌入设计布局中，通过用顶部布局的数字布局实例替换数字布局块的数字实例模块的设计布局。

3. 发明申请

WO2007044018A3 METHODS OF MODEL COMPILATION 审中-公开
标题翻译：模式编译方法
公开(公告)号：WO2007044018A3
公开(公告)日：2009-04-16
申请号：PCT/US2005037605
申请日：2005-10-20
申请人： CADENCE DESIGN SYSTEMS INC , KUNDERT KENNETH S
发明人： KUNDERT KENNETH S
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036 , G06F8/41
摘要： A method ( 200 ) is provided for compiling a model for use in a simulation, the method comprising receiving a description of the model ( 202 ); and automatically converting the description into an implementation of the model (204 ) that is customized for a selected analysis during simulation.
摘要翻译：提供了一种用于编译用于模拟的模型的方法（200），所述方法包括接收所述模型（202）的描述; 并自动将描述转换成在模拟期间针对所选择的分析定制的模型（204）的实现。

4. 发明申请

WO2007078915A3 SYSTEM AND METHOD FOR GENERATING A PLURALITY OF MODELS AT DIFFERENT LEVELS OF ABSTRACTION FROM A SINGLE MASTER MODEL 审中-公开
标题翻译：用于从单个主模型生成不同级别的抽样的多样性模型的系统和方法
公开(公告)号：WO2007078915A3
公开(公告)日：2009-04-09
申请号：PCT/US2006048249
申请日：2006-12-18
申请人： CADENCE DESIGN SYSTEMS INC , WATANABE YOSHINORI , LAVAGNO LUCIANO , KONDRATYEV ALEX
发明人： WATANABE YOSHINORI , LAVAGNO LUCIANO , KONDRATYEV ALEX
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505
摘要： A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each other, and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.
摘要翻译：一种产生硬件（集成电路）设计的多个模型的方法，包括：将集成电路的设计的主模型转换为在功能上等同于主模型并且处于不同抽象级别的至少第一和第二模型并且其中第一和第二模型中的每一个包括针对其抽象级别准确的集成电路定时信息。

5. 发明申请

WO2008030688A1 AUTO-DETECTING AND DOWNLOADING LICENSED COMPUTER PRODUCTS 审中-公开
标题翻译：自动检测和下载许可的计算机产品
公开(公告)号：WO2008030688A1
公开(公告)日：2008-03-13
申请号：PCT/US2007/075833
申请日：2007-08-13
申请人： CADENCE DESIGN SYSTEMS, INC. , NIAKAN, Nima , LO, Lindy , BAEDER, Scott
发明人： NIAKAN, Nima , LO, Lindy , BAEDER, Scott
IPC分类号： G06F21/00
CPC分类号： G06F21/105
摘要： In a system and method for automatically detecting licensed computer products, a license manager stores contract data indicating a customer and one or more computer products licensed to the customer by a license holder. A customer site is automatically checked for present computer products owned by the license holder. The licensed computer products are compared to the present computer products. In one embodiment, the computer products are software products, but they also may be hardware products.
摘要翻译：在用于自动检测许可计算机产品的系统和方法中，许可证管理器存储指示客户的合同数据和由许可证持有者许可给客户的一个或多个计算机产品。客户站点自动检查许可证持有者拥有的电脑产品。将许可的计算机产品与当前的计算机产品进行比较。在一个实施例中，计算机产品是软件产品，但它们也可以是硬件产品。

6. 发明申请

WO2007147147A2 METHOD AND APPARATUS FOR APPROXIMATING DIAGONAL LINES IN PLACEMENT 审中-公开
标题翻译：用于对置放置对角线的方法和装置
公开(公告)号：WO2007147147A2
公开(公告)日：2007-12-21
申请号：PCT/US2007071397
申请日：2007-06-15
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K
发明人： SCHEFFER LOUIS K
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Some embodiments of the invention provide a method for placing circuit modules in an integrated circuit ("IC") layout. The method computes a placement metric for the IC layout. In some embodiments, computing the placement metric includes partitioning a region the IC layout into several sub-regions by using a cut graph, where the cut graph is an approximation of a diagonal cut line. These embodiments then generate congestion-cost estimates by measuring the number of nets cut by the cut graph. In some embodiments, the cut graph is a staircase cut graph. These staircase cut graphs include several horizontal and vertical cut lines. In some embodiments, the cut graph is a cut arc.
摘要翻译：本发明的一些实施例提供了一种将电路模块放置在集成电路（“IC”）布局中的方法。该方法计算IC布局的布局度量。在一些实施例中，计算布局度量包括通过使用切割图将IC布局的区域划分成若干子区域，其中切割图是对角线切割线的近似。这些实施例然后通过测量由切割图切割的网络的数量来产生拥塞成本估计。在一些实施例中，切割图是梯形切割图。这些楼梯切割图包括几条水平和垂直切割线。在一些实施例中，切割图是切割弧。

7. 发明申请

WO2007120888A2 SIMULATION OF POWER DOMAIN ISOLATION 审中-公开
标题翻译：电力域隔离的模拟
公开(公告)号：WO2007120888A2
公开(公告)日：2007-10-25
申请号：PCT/US2007/009277
申请日：2007-04-12
申请人： CADENCE DESIGN SYSTEMS, INC. , CHEN, Yonghao
发明人： CHEN, Yonghao
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register- transfer-level (RTL) design environment, receiving power information specifications of the circuit, associating the plurality of power domains and the power information specifications in the RTL design environment, where the plurality of power domains are controlled by a set of power control signals through a power manager logic, isolating a power domain among the plurality of power domains for simulation, and simulating isolation behavior of the power domain in response to variations in power applied to the power domain.
摘要翻译：公开了用于模拟功率域隔离的方法和系统。该方法包括：接收在注册转换级（RTL）设计环境中表示的电路的网表描述，接收电路的功率信息规范，将多个电源域和功率信息规范相关联，并将其与RTL设计环境，其中通过功率管理器逻辑通过一组功率控制信号来控制多个功率域，隔离多个功率域中的功率域进行模拟，以及响应于施加的功率变化来模拟功率域的隔离行为到电力领域。

8. 发明申请

WO2006127538A3 MANUFACTURING AWARE DESIGN AND DESIGN AWARE MANUFACTURING 审中-公开
标题翻译：制造设计和设计意识制造
公开(公告)号：WO2006127538A3
公开(公告)日：2007-04-05
申请号：PCT/US2006019624
申请日：2006-05-20
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K , FUJIMURA AKIRA
发明人： SCHEFFER LOUIS K , FUJIMURA AKIRA
IPC分类号： G06F17/50 , G03C5/00 , G03F1/00 , G06K9/62
CPC分类号： G06F17/5068 , G03F7/70091 , G03F7/70125 , G03F7/70425 , G05B2219/35028 , G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit ("IC") layout (1205). The process receives a manufacturing configuration that specifies a set of manufacturing settings (1210) for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules (1215) based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout (1225). Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit ("IC") (1227). The process receives an IC desig with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings (1230).
摘要翻译：本发明的一些实施例提供了一种用于设计集成电路（“IC”）布局（1205）的制造感知过程。该过程接收制造配置，其指定用于基于IC布局用于制造IC的一组机器的一组制造设置（1210）。该过程基于指定的制造配置来定义一组设计规则（1215）。该过程使用一组设计规则来设计IC布局（1225）。本发明的一些实施例提供了一种用于制造集成电路（“IC”）的设计感知过程（1227）。该过程接收具有相关联的一组设计属性的IC设计。该过程指定制造配置，其指定用于制造IC的一组机器的一组制造设置，其中指定的一组制造设置基于该组设计属性。该过程基于制造设置制造IC（1230）。

9. 发明申请

WO2006127408A3 METHOD AND SYSTEM FOR INCREASED ACCURACY FOR EXTRACTION OF ELECTRICAL PARAMETERS 审中-公开
标题翻译：用于提取电气参数的提高精度的方法和系统
公开(公告)号：WO2006127408A3
公开(公告)日：2007-03-15
申请号：PCT/US2006019304
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K , STAUD WOLFGANG H , HUCKABAY JUDY
发明人： SCHEFFER LOUIS K , STAUD WOLFGANG H , HUCKABAY JUDY
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An improved method, system, and computer program product is disclosed for increased accuracy for extraction of electrical parameters of an IC design. Extraction is performed upon the expected geometric model of the printed layout once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for performing extraction since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The extracted electrical parameters are checked for acceptability. If not acceptable, then the IC design can be modified to address any identified problems or desired improvements to the design.
摘要翻译：公开了一种改进的方法，系统和计算机程序产品，用于提高IC设计的电参数的精度。一旦制造和平版印刷过程效果被考虑，就按照打印布局的预期几何模型进行提取。这提供了一种更精确的执行提取方法，因为它是被分析的实际预期几何形状，而不是不能准确对应于实际制造的IC产品的理想化模型。检查提取的电气参数是否可接受。如果不能接受，则可以修改IC设计以解决任何已识别的问题或对设计的期望改进。

10. 发明申请

WO2006127409A2 SYSTEM AND METHOD FOR STATISTICAL DESIGN RULE CHECKING 审中-公开
标题翻译：统计设计规则检查系统与方法
公开(公告)号：WO2006127409A2
公开(公告)日：2006-11-30
申请号：PCT/US2006/019305
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS, INC. , SCHEFFER, Louis K.
发明人： SCHEFFER, Louis K.
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Methods and systems for allowing an Integrated Circuit designer to specify one or more design rules, and to determine the expected probability of success of the IC design based on the design rules. Probability information is compiled for each circuit component, that specifies the probability of the circuit component working if a characteristic of the circuit component is varied. As the design rules are examined, the probability of each component working is calculated. The probabilities are combined to determine the overall probability of success for the IC design. Furthermore, the IC design may be broken into a plurality of portions, and design rules can be separately specified for each portion. This allows a designer the flexibility to use different design rules on different portions of the IC design.
摘要翻译：允许集成电路设计者指定一个或多个设计规则的方法和系统，并且基于设计规则确定IC设计成功的预期概率。针对每个电路组件编制概率信息，其指定电路组件的特性如果变化时电路组件工作的概率。随着设计规则的检验，每个部件工作的概率被计算出来。将概率相结合以确定IC设计的成功概率。此外，IC设计可以被分成多个部分，并且可以为每个部分分别指定设计规则。这允许设计人员灵活地在IC设计的不同部分使用不同的设计规则。

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