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    • 5. 发明申请
    • APPARATUS AND METHOD FOR RE-EXECUTION OF FAULTING OPERATIONS
    • 用于重新执行失败操作的装置和方法
    • WO2017172297A1
    • 2017-10-05
    • PCT/US2017/021108
    • 2017-03-07
    • INTEL CORPORATION
    • HILDESHEIM, GurYANOVER, IgorSHWARTSMAN, StanislavSADE, RaananRAIS, Ron
    • G06F9/30G06F9/48
    • An apparatus and method are described for at-retirement re-execution of faulting operations. For example, one embodiment of a processor comprises: an out-of-order engine to schedule and dispatch operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory; a first circuit to determine whether a current load/store operation is at retirement; a second circuit to cause logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement, wherein upon detection of a fault condition associated with the load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers, the second circuit to cause the logging circuitry and/or fault registers to be inactive if the load/store operation has not be dispatched at retirement.
    • 描述了用于退役重新执行错误操作的装置和方法。 例如,处理器的一个实施例包括:无序引擎,用于调度和分派操作给执行单元,至少一些操作包括加载操作以加载来自系统存储器的数据并存储操作以将数据存储到 系统内存; 确定当前加载/存储操作是否在退休的第一电路; 第二电路,用于在退役时已经调度加载/存储操作时使得日志记录电路和/或故障寄存器有效,其中在检测到与加载/存储操作相关联的故障状况时,与故障相关联的数据将是 写入记录电路和/或故障寄存器,如果加载/存储操作在退役时未被调度,则第二电路使得记录电路和/或故障寄存器不活动。
    • 6. 发明申请
    • APPARATUS AND METHOD FOR A DIGITAL NEUROMORPHIC PROCESSOR
    • 用于数字神经形态处理器的装置和方法
    • WO2017172295A1
    • 2017-10-05
    • PCT/US2017/021084
    • 2017-03-07
    • INTEL CORPORATION
    • CHEN, Gregory K.SEO, Jae-SunCHEN, Thomas C.KUMAR, Raghavan
    • G06N3/06G06N3/04G06N3/063G06N99/00
    • G06N3/063G06N3/049
    • An apparatus and method are described for a neuromorphic processor design in which neuron timing information is duplicated on a neuromorphic core. For example, one embodiment of an apparatus comprises: a first neurosynaptic core comprising a plurality of neurons and a synapse array comprising a plurality of synapses to communicatively couple the plurality of neurons, each synapse connecting two neurons having a weight associated therewith, wherein a first neuron is to generate an output spike based on the weights of synapses over which inputs are received from the other neurons; a second neurosynaptic core also comprising a plurality of neurons and having at least one counter to maintain a count value indicative of spike timing for a second neuron, wherein a spike output of the second neuron in the second neurosynaptic core is communicatively coupled over a first synapse to the first neuron in the first neurosynaptic core; and a duplicate counter maintained within the first neurosynaptic core and synchronized with the counter from the second neurosynaptic core, the first neuron to use a first value from the duplicate counter to adjust the weight of the first synapse coupling the second neuron to the first neuron.
    • 描述了用于神经形态处理器设计的装置和方法,其中神经元定时信息在神经形态核心上被复制。 例如,装置的一个实施方案包括:包含多个神经元的第一神经突触核心和包含多个突触的突触阵列,以通信地耦合多个神经元,每个突触连接两个神经元,所述两个神经元具有与其相关联的重量,其中第一 神经元将基于从其他神经元接收输入的突触的权重产生输出尖峰; 第二神经突触核心还包括多个神经元并且具有至少一个计数器以维持指示第二神经元的尖峰计时的计数值,其中第二神经突触核心中的第二神经元的尖峰输出在第一突触上通信地偶联 到第一个神经突触核心的第一个神经元; 以及保持在第一神经突触核心内并与来自第二神经突触核心的计数器同步的复制计数器,第一神经元使用来自复制计数器的第一值来调整将第二神经元耦合到第一神经元的第一突触的权重。