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1. 发明申请

WO2021069943A1 SELF-ADAPTIVE WEAR LEVELING METHOD AND ALGORITHM 审中-公开
公开(公告)号：WO2021069943A1
公开(公告)日：2021-04-15
申请号：PCT/IB2019/000970
申请日：2019-10-09
申请人： MICRON TECHNOLOGY, INC.
发明人： FERRANTE, Gianfranco , BALLUCHI, Daniele , MINOPOLI, Dionisio
IPC分类号： G06F12/02
摘要： The present disclosure relates to a method for data relocation in memory having two portions of data. An embodiment includes a memory having a plurality of physical blocks of memory cells, and a first and second portion of data having a first and second, respectively, number of logical block addresses associated therewith. Two of the plurality of physical blocks of cells do not have data stored therein. In the method, the data of the first portion that is associated with one of the first number of logical block addresses is relocated to one of the two physical blocks of cells that don't have data stored therein, and the data of the second portion that is associated with one of the second number of logical block addresses is relocated to the other one of the two physical blocks of cells that don't have data stored therein.

2. 发明申请

WO2020240235A1 CONTROLLER FOR A MEMORY COMPONENT 审中-公开
公开(公告)号：WO2020240235A1
公开(公告)日：2020-12-03
申请号：PCT/IB2019/000478
申请日：2019-05-31
申请人： MICRON TECHNOLOGY, INC
发明人： TROIA, Alberto , MONDELLO, Antonino
IPC分类号： G06F9/445
摘要： A controller for a memory component comprises a processing unit and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; the processing unit is configured to capture a memory address of a program instruction to be executed, compare the memory address with a reference value, and, based on that comparison, enable /restricting actions associated with the program instruction. A related memory component and related methods are also disclosed.

3. 发明申请

WO2020240229A1 JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION 审中-公开
公开(公告)号：WO2020240229A1
公开(公告)日：2020-12-03
申请号：PCT/IB2019/000467
申请日：2019-05-31
申请人： MICRON TECHNOLOGY, INC.
发明人： TROIA, Alberto , MONDELLO, Antonino
IPC分类号： G11C29/16 , G11C29/48
摘要： The present disclosure relates to an apparatus comprising a memory component having an independent structure and including at least an array of memory cells with associated decoding and sensing circuitry, a host device coupled to the memory component through at least a communication channel, a control and JTAG interface in said at least an array of memory cells, and at least an additional register in said control and JTAG interface for handing data, addresses and control signals provided by the host device. The additional register is configured to store at least a page address associated with the array of memory cells, the memory component is configured to load said page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at said page address. A corresponding non-volatile memory device and method are disclosed.

4. 发明申请

WO2020157529A1 MEMORY DEVICE AND METHOD FOR MANAGING THE SAME 审中-公开
公开(公告)号：WO2020157529A1
公开(公告)日：2020-08-06
申请号：PCT/IB2019/000010
申请日：2019-01-29
申请人： MICRON TECHNOLOGY, INC.
发明人： TROIA, Alberto , REINA, Vincenzo
IPC分类号： G11C7/20 , G11C16/34
摘要： The present disclosure relates to a method for managing a memory device including a non-volatile memory, the method comprising providing a first time-stamp to the memory device, wherein the first time-stamp is a power-down time-stamp of the memory device, storing the first time-stamp, associating the first time-stamp with at least one region of the non-volatile memory, providing a second time-stamp to the memory device, wherein the second time-stamp is a subsequent power-up time-stamp of the memory device, associating the second time-stamp with said at least one region of the non-volatile memory, determining a difference time between the first time-stamp and the second time-stamp, and, based on said difference time, performing a refresh operation of said at least one region of the non-volatile memory. A related memory device is also disclosed, as well as a specific method for measuring the off-time of a memory device.

5. 发明申请

WO2012094481A2 MEMORY ADDRESS TRANSLATION 审中-公开
标题翻译：存储器地址转换
公开(公告)号：WO2012094481A2
公开(公告)日：2012-07-12
申请号：PCT/US2012/020312
申请日：2012-01-05
申请人： MICRON TECHNOLOGY, INC. , MANNING, Troy, A. , CULLEY, Martin, L. , LARSEN, Troy, D.
发明人： MANNING, Troy, A. , CULLEY, Martin, L. , LARSEN, Troy, D.
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02D10/13
摘要： The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
摘要翻译：本公开包括用于存储器地址转换的设备，系统和方法。一个或多个实施例包括存储器阵列和耦合到阵列的控制器。该阵列包括具有多个记录的第一表格，其中每个记录包括多个条目，其中每个条目包括与存储在阵列中的数据段相对应的物理地址和逻辑地址。控制器包括具有多个记录的第二表格，其中每个记录包括多个条目，其中每个条目包括对应于第一表格中的记录的物理地址和逻辑地址。控制器还包括具有多个记录的第三表格，其中每个记录包括多个条目，其中每个条目包括对应于第二表格中的记录的物理地址和逻辑地址。

6. 发明申请

WO2011133205A2 VERTICAL TRANSISTOR PHASE CHANGE MEMORY 审中-公开
标题翻译：垂直晶体管相位变化记忆
公开(公告)号：WO2011133205A2
公开(公告)日：2011-10-27
申请号：PCT/US2011/000650
申请日：2011-04-11
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun
发明人： LIU, Jun
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/249 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/124 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor.
摘要翻译：本文描述了垂直晶体管相变存储器和处理相变存储器的方法。一种或多种方法包括在垂直晶体管的至少一部分上形成电介质，在电介质上形成电极，并且在电极侧面的一部分和侧面的一部分上形成垂直条状的相变材料的电介质沿着电极延伸并且电介质与垂直晶体管接触。

7. 发明申请

WO2011043791A2 STRIPE-BASED MEMORY OPERATION 审中-公开
标题翻译：基于条带的内存操作
公开(公告)号：WO2011043791A2
公开(公告)日：2011-04-14
申请号：PCT/US2010/002556
申请日：2010-09-20
申请人： MICRON TECHNOLOGY, INC. , JEDDELOH, Joseph, M.
发明人： JEDDELOH, Joseph, M.
IPC分类号： G06F13/10 , G06F12/00
CPC分类号： G06F11/08 , G06F3/0616 , G06F3/064 , G06F3/0688 , G06F11/1028 , G06F11/108
摘要： The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.
摘要翻译：本公开包括用于基于条带的存储器操作的方法和设备。一个方法实施例包括跨越多个存储器设备的存储卷在第一条带中写入数据。第一条带的一部分通过在跨多个存储器装置的存储卷的第二条带的一部分中写入更新的数据而被更新。第一个条纹的部分无效。保持第一条带的无效部分和第一条带的其余部分，直到第一条带被回收。其他方法和设备也被披露。

8. 发明申请

WO2011019372A3 PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL 审中-公开
公开(公告)号：WO2011019372A3
公开(公告)日：2011-02-17
申请号：PCT/US2010/002186
申请日：2010-08-06
申请人： MICRON TECHNOLOGY, INC. , RADKE, William, H. , TSAI, Victor, Y. , FEELEY, Peter , GALBO, Neal, A. , LEIBOWITZ, Robert, N.
发明人： RADKE, William, H. , TSAI, Victor, Y. , FEELEY, Peter , GALBO, Neal, A. , LEIBOWITZ, Robert, N.
IPC分类号： H04L12/56 , H04L29/06
摘要： The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.

9. 发明申请

WO2010101609A2 MEMORY BLOCK MANAGEMENT 审中-公开
标题翻译：内存块管理
公开(公告)号：WO2010101609A2
公开(公告)日：2010-09-10
申请号：PCT/US2010/000540
申请日：2010-02-24
申请人： MICRON TECHNOLOGY, INC. , ASNAASHARI, Mehdi , CHEN, Alan , NEMAZIE, Siamack
发明人： ASNAASHARI, Mehdi , CHEN, Alan , NEMAZIE, Siamack
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7209 , G11C29/76
摘要： Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.
摘要翻译：各种实施例包括具有组织成超块的物理块的至少两个平面的一个或多个存储器件，每个超级块包括来自至少两个平面中的每一个的物理块。实施例包括确定平面内的有缺陷的块。如果没有将特定块位置处的块都确定为有缺陷，则实施例包括将特定块位置处的块分配给超块，并且如果确定特定块位置处的一个或多个块被确定为有缺陷，实施例包括：将确定为有缺陷的特定块位置的块分配给超块; 以及针对被确定为有缺陷的特定块位置处的所述一个或多个块中的每个块为所述超级块分配相应的替换块。相应的替换块从包括被确定为有缺陷的相应块的平面中的相应一个中的多个块中选择。

10. 发明申请

WO2010090696A2 LOGICAL ADDRESS OFFSET 审中-公开
标题翻译：逻辑地址偏移
公开(公告)号：WO2010090696A2
公开(公告)日：2010-08-12
申请号：PCT/US2010/000095
申请日：2010-01-15
申请人： MICRON TECHNOLOGY, INC. , ASNAASHARI, Mehdi , BENSON, William, E.
发明人： ASNAASHARI, Mehdi , BENSON, William, E.
IPC分类号： G06F12/02
CPC分类号： G06F12/06 , G06F3/0608 , G06F3/0638 , G06F3/0679 , G06F12/0246 , G06F2212/7202
摘要： The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.
摘要翻译：本公开包括用于逻辑地址偏移的方法，设备和系统。一个方法实施例包括检测存储单元格式化操作。随后，响应于检测到格式化操作，该方法包括检查存储器单元上的格式信息，计算逻辑地址偏移量，并将该偏移量应用于主机逻辑地址。

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