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71. 发明申请

WO2006011962A1 THREAD SYNCHRONIZATION WITH LOCK INFLATION METHODS AND APPARATUS FOR MANAGED RUN-TIME ENVIRONMENTS 审中-公开
标题翻译：具有锁定充电方法的线程同步和管理的运行环境的设备
公开(公告)号：WO2006011962A1
公开(公告)日：2006-02-02
申请号：PCT/US2005/020548
申请日：2005-06-10
申请人： INTEL CORPORATION (a Delaware Coprporation) , SHPEISMAN, Tatiana , ADL-TABATABAI, Ali-Reza , MURPHY, Brian
发明人： SHPEISMAN, Tatiana , ADL-TABATABAI, Ali-Reza , MURPHY, Brian
IPC分类号： G06F9/52
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/52 , Y10S707/99938
摘要： Thread synchronization with lock inflation methods and apparatus for managed run-time environments are disclosed. An example method disclosed herein comprises determining a locking operation to perform on a lock corresponding to the object, performing an optimistically balanced synchronization of the lock if the locking operation is not unbalanced, and modifying a lock shape of the lock if the locking operation is unbalanced.
摘要翻译：公开了具有用于管理的运行时环境的锁定充气方法和装置的线程同步。本文公开的示例性方法包括确定对与对象相对应的锁执行的锁定操作，如果锁定操作不是不平衡则执行锁的乐观平衡的同步，以及如果锁定操作不平衡则修改锁的形状。

72. 发明申请

WO2005071550A2 MULTI-PROCESSOR COMPUTING SYSTEM THAT EMPLOYS COMPRESSED CACHE LINES' WORTH OF INFORMATION AND PROCESSOR CAPABLE OF USE IN SAID SYSTEM 审中-公开
标题翻译：多处理器计算系统，使用压缩的缓存线路可以在系统中使用的信息和处理器
公开(公告)号：WO2005071550A2
公开(公告)日：2005-08-04
申请号：PCT/US2005000797
申请日：2005-01-10
申请人： INTEL CORP , NEWBURN CHRIS , HUGGAHALLI RAM , HUM HERBERT , ADL-TABATABAI ALI-REZA , GHULOUM ANWAR
发明人： NEWBURN CHRIS , HUGGAHALLI RAM , HUM HERBERT , ADL-TABATABAI ALI-REZA , GHULOUM ANWAR
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0886 , G06F12/0802 , G06F12/0864 , G06F2212/401
摘要： Cache coherency rules for a multi-processor computing system that is capable of working with compressed cache lines' worth of information are described. A multi-processor computing system that is capable of working with compressed cache lines' worth of information is also described. The multi-processor computing system includes a plurality of hubs for communicating with various computing system components and for compressing/decompressing cache lines' worth of information. A processor that is capable of labeling cache lines' worth of information in accordance with the cache coherency rules is described. A processor that includes a hub as described above is also described.
摘要翻译：描述了能够处理压缩高速缓存行的信息量的多处理器计算系统的缓存一致性规则。还描述了能够处理压缩高速缓存行的信息的多处理器计算系统。多处理器计算系统包括用于与各种计算系统组件进行通信并用于压缩/解压缩高速缓存行的信息价值的多个集线器。描述了能够根据高速缓存一致性规则来标记高速缓存线值的信息的处理器。还描述了包括如上所述的集线器的处理器。

73. 发明申请

WO2005066791A1 DYNAMIC PERFORMANCE MONITORING-BASED APPROACH TO MEMORY MANAGEMENT 审中-公开
标题翻译：基于动态性能监控的记忆管理方法
公开(公告)号：WO2005066791A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/043349
申请日：2004-12-24
申请人： INTEL CORPORATION , SUBRAMONEY, Sreevinas , HUDSON, Richard , SERRANO, Mauricio , ADL-TABATABAI, Ali-Reza
发明人： SUBRAMONEY, Sreevinas , HUDSON, Richard , SERRANO, Mauricio , ADL-TABATABAI, Ali-Reza
IPC分类号： G06F12/02
CPC分类号： G06F11/348 , G06F12/0253 , G06F12/0269 , G06F2201/88 , G06F2201/885 , Y10S707/99957
摘要： Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.
摘要翻译：描述了用于优化处理器系统中的存储器管理的技术。这些技术可以在包括片上性能监视的处理器以及外部性能监视器耦合到处理器的系统上实现。包括性能监控单元（PMU）的处理器就是例子。 PMU可以将数据存储在读取和写入高速缓存未命中，以及翻译后备缓冲区（TLB）未命中的数据。来自PMU的数据用于确定存储器堆中的任何存储器区域是否是过期存储器区域，即表现出大量存储器问题或失速的区域。如果发现存在不正当的内存区域，诸如垃圾收集例程的存储器管理器可以通过改进堆中对象的布局来有效地优化存储器性能以及突变器的性能。以这种方式，可以基于动态和实时存储器性能数据来集中存储器管理例程。

74. 发明申请

WO2005004336A3 ADAPTIVE JOINT SOURCE CHANNEL CODING 审中-公开
公开(公告)号：WO2005004336A3
公开(公告)日：2005-01-13
申请号：PCT/US2004/020795
申请日：2004-06-28
申请人： SONY ELECTRONICS, INC. , CHOU, Jim, Chen , TABATABAI, Ali, Tezu
发明人： CHOU, Jim, Chen , TABATABAI, Ali, Tezu
IPC分类号： H04B1/66
摘要： Adaptive joint source channel coding associates multiple predictors with a reference data unit, such as a macroblock or frame data. An encoder (201) determines a sub-codebook in which each of the selected multiple predictors (209, 211, 213, 215) decodes to the reference data unit (207). An identifier for the sub-codebook is transmitted through a channel (203) to a decoder (205) for subsequent decoding of the reference data unit. The reference data unit itself does not need to be sent. The multiple predictors are contained within a decoding region (219) and the identifier for the sub-codebook specifies the decoding region. The decoder uses the identified uses the identified sub-codebook and one of the predictors to decode the reference data unit. If none of the original predictors are correctly received, different types of error handling are employed based on the type of channel.

75. 发明申请

WO2016201145A1 DATA-CHARGE PHASE DATA COMPRESSION ARCHITECTURE 审中-公开
标题翻译：数据充电阶段数据压缩架构
公开(公告)号：WO2016201145A1
公开(公告)日：2016-12-15
申请号：PCT/US2016/036767
申请日：2016-06-09
申请人： SONY CORPORATION , CHEONG, Hye-Yeon , IKEDA, Masaru , TABATABAI, Ali
发明人： CHEONG, Hye-Yeon , IKEDA, Masaru , TABATABAI, Ali
IPC分类号： H04N19/159 , H04N19/13 , H04N19/124 , H04N19/50
CPC分类号： H04N19/124 , H04N19/11 , H04N19/129 , H04N19/13 , H04N19/159 , H04N19/172 , H04N19/176 , H04N19/192 , H04N19/593
摘要： Implementations generally relate to data-charge phase data compression. In one implementation, a method includes computing prediction values for image data, where the image data is data-charge phase data, and where the computing of prediction values is based on inter-block prediction. The method also includes computing residual data based on the prediction values. The method also includes quantizing the residual data. The method also includes entropy encoding the quantized residual data. The method also includes refining an inverse quantized residual data based on one or more of the residual data and a number of left-over bit-budget after entropy encoding.
摘要翻译：实现通常涉及数据充电阶段数据压缩。在一个实现中，一种方法包括计算图像数据的预测值，其中图像数据是数据充电相位数据，并且其中预测值的计算基于块间预测。该方法还包括基于预测值来计算残差数据。该方法还包括量化剩余数据。该方法还包括对量化的残差数据进行熵编码。该方法还包括基于熵编码之后的剩余数据和剩余比特预算中的一个或多个来精炼逆量化残差数据。

76. 发明申请

WO2015191263A1 COMMUNICATION SYSTEM WITH CODING MECHANISM AND METHOD OF OPERATION THEREOF 审中-公开
标题翻译：具有编码机制的通信系统及其操作方法
公开(公告)号：WO2015191263A1
公开(公告)日：2015-12-17
申请号：PCT/US2015/031764
申请日：2015-05-20
申请人： SONY CORPORATION , CHEONG, Hye-Yeon , TABATABAI, Ali
发明人： CHEONG, Hye-Yeon , TABATABAI, Ali
IPC分类号： H03M7/40
CPC分类号： H04N19/176 , H03M7/4075 , H04N19/91
摘要： A communication system and the method of operation thereof includes: a block size unit for receiving an input digital data stream; a progressive-Golomb encoder, coupled to the block size unit, for encoding a progressive-Golomb codeword from the input digital data stream; and a transmitter unit, coupled to the progressive-Golomb encoder for transferring the progressive-Golomb codeword to an output device.
摘要翻译：通信系统及其操作方法包括：块大小单元，用于接收输入的数字数据流; 耦合到块大小单元的渐进哥伦布编码器，用于对来自输入数字数据流的渐进哥伦布码字进行编码; 以及耦合到渐进式哥伦布编码器的发射机单元，用于将渐进哥伦布码字传送到输出设备。

77. 发明申请

WO2015006281A3 INTER-LAYER PREDICTION SHVC/MV-HEVC SYNTAX IMPROVEMENT 审中-公开
公开(公告)号：WO2015006281A3
公开(公告)日：2015-01-15
申请号：PCT/US2014/045677
申请日：2014-07-08
申请人： SONY CORPORATION , XU, Jun , TABATABAI, Ali
发明人： XU, Jun , TABATABAI, Ali
IPC分类号： H04N7/26 , H04N7/30 , H04N19/50
摘要： Syntax changes for SHVC/MV-HEVC coding apparatus and methods are described which improve efficiency. In a first portion, syntax of header signaling position under P or B-slice conditions are described, and a new condition to signal inter-layer prediction layer. A second portion describes use of an inter-layer reference picture set as an alternative to the first portion, and provides an arranged syntax to more efficiently signal inter-layer reference information. In a third portion, an inter-layer sample only prediction and TMVP interaction is described which reduces signaling needs for collocated references syntax.

78. 发明申请

WO2013109360A2 FLEXIBLE BAND OFFSET MODE IN SAMPLE ADAPTIVE OFFSET IN HEVC 审中-公开
标题翻译： HEVC中样品自适应偏移中的柔性带偏移模式
公开(公告)号：WO2013109360A2
公开(公告)日：2013-07-25
申请号：PCT/US2012/069024
申请日：2012-12-11
申请人： SONY CORPORATION , MAANI, Ehsan , TABATABAI, Ali , XU, Jun
发明人： MAANI, Ehsan , TABATABAI, Ali , XU, Jun
IPC分类号： H04N7/26
CPC分类号： H04N19/44 , H04N19/117 , H04N19/14 , H04N19/176 , H04N19/50 , H04N19/61 , H04N19/82 , H04N19/86 , H04N19/96
摘要： A Flexible Band Offset (FBO) apparatus and method of performing Sample Adaptive Offset (SAO) filtering within encoders and decoders, such as according to the High Efficiency Video Coding (HEVC) standard, and similarly configured coding devices. The number of Band Offset (BO) modes and the number of necessary offsets is reduced. The invention beneficially provides simpler coding, reduces temporary buffer size requirements, and can yield a small performance gain over existing SAO techniques of HEVC test model HM 5.
摘要翻译：一种灵活的带偏移（FBO）装置和方法，用于根据高效率视频编码（HEVC）标准和类似配置的编码装置在编码器和解码器内执行采样自适应偏移（SAO）滤波。减少了带宽偏移（BO）模式的数量和必要的偏移量。本发明有利地提供了更简单的编码，减少了临时缓冲区大小的要求，并且与现有的HEVC测试模型HM5的SAO技术相比可以产生小的性能增益。

79. 发明申请

WO2013006406A3 METHOD AND SYSTEM FOR SAFE ENQUEUING OF EVENTS 审中-公开
标题翻译：安全事件的方法和系统
公开(公告)号：WO2013006406A3
公开(公告)日：2013-03-28
申请号：PCT/US2012044837
申请日：2012-06-29
申请人： INTEL CORP , FARRELL ROBERT L , ADL-TABATABAI ALI-REZA , KOKER ALTUG
发明人： FARRELL ROBERT L , ADL-TABATABAI ALI-REZA , KOKER ALTUG
IPC分类号： G06F9/06 , G06F9/44
CPC分类号： G06F9/544 , G06F9/545
摘要： A method and system to facilitate a user level application executing in a first processing unit to enqueue work or task(s) safely for a second processing unit without performing any ring transition. For example, in one embodiment of the invention, the first processing unit executes one or more user level applications, where each user level application has a task to be offloaded to a second processing unit. The first processing unit signals the second processing unit to handle the task from each user level application without performing any ring transition in one embodiment of the invention.
摘要翻译：一种促进在第一处理单元中执行的用户级应用程序以对第二处理单元安全地排队工作或任务而不执行任何环转换的方法和系统。例如，在本发明的一个实施例中，第一处理单元执行一个或多个用户级应用，其中每个用户级应用具有卸载到第二处理单元的任务。在本发明的一个实施例中，第一处理单元用信号通知第二处理单元来处理来自每个用户级应用的任务而不执行任何环转移。

80. 发明申请

WO2011081719A2 PERFORMING MODE SWITCHING IN AN UNBOUNDED TRANSACTIONAL MEMORY (UTM) SYSTEM 审中-公开
标题翻译：在无界的事务存储器（UTM）系统中执行模式切换
公开(公告)号：WO2011081719A2
公开(公告)日：2011-07-07
申请号：PCT/US2010/056172
申请日：2010-11-10
申请人： INTEL CORPORATION , ADL-TABATABAI, Ali-Reza , SAHA, Bratin , BASSIN, Vadim , SHEAFFER, Gad , GRAY, Jan , GROVER, Vinod , TAILLEFER, Martin , LEVANONI, Yossi , DETLEFS, Dave , MAGRUDER, Mike , TOLTON, Matt
发明人： ADL-TABATABAI, Ali-Reza , SAHA, Bratin , BASSIN, Vadim , SHEAFFER, Gad , GRAY, Jan , GROVER, Vinod , TAILLEFER, Martin , LEVANONI, Yossi , DETLEFS, Dave , MAGRUDER, Mike , TOLTON, Matt
IPC分类号： G06F13/14 , G06F12/08
CPC分类号： G06F12/0815 , G06F9/467 , G06F11/141
摘要： In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于选择第一事务执行模式以在具有多个事务执行模式的无界事务存储器（UTM）系统中开始第一事务的方法。这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件和软件缓冲器执行的硬件辅助模式以及在没有事务硬件的情况下执行的软件事务存储器（STM）模式。如果在STM模式中未执行未决事务，则可选择第一事务执行模式作为硬件模式的最高性能，否则可选择较低性能模式。描述并要求保护其他实施例。

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