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71. 发明申请

WO2005029262A2 A METHOD FOR GENERATING OPTIMIZED CONSTRAINT SYSTEMS FOR RETIMABLE DIGITAL DESIGNS 审中-公开
标题翻译：用于生成可反复数字设计的优化约束系统的方法
公开(公告)号：WO2005029262A2
公开(公告)日：2005-03-31
申请号：PCT/US2004030409
申请日：2004-09-17
申请人： CADENCE DESIGN SYSTEMS INC
发明人： GIDON ALEXANDER , KNAPP DAVID
IPC分类号： G06F20060101 , G06F7/38 , G06F17/50 , G06F
CPC分类号： G06F17/505
摘要： A method for generating timing constraint systems, where the constrained object is a digital circuit., is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit.
摘要翻译：提供了一种用于产生定时约束系统的方法，其中约束对象是数字电路，其中为使用数字逻辑优化（综合）工具生成约束。该合成工具用于在施加的约束条件下优化电路，使得电路具有某些期望的时序特性，同时最小化硬件成本和各种其它特性。当所述电路在优化之后被重新定时时，由所公开的发明产生的特定类别的时序约束是有用的。通常，联合使用所描述的发明和重新定时导致设计的整体成本/性能折衷曲线的改进。本发明包括一种方法，其包括以下步骤：（1）设计的触发器被具有负延迟的缓冲器替换，其幅度近似为设计的期望时钟周期时间; 并且（2）设计中的周期使用具有无限或准无限时钟频率的触发器来断开。通过综合工具进行优化后，可以恢复临时更改，并对电路进行重新定时。

72. 发明申请

WO2004104871A2 INTEGRATED PROOF FLOW SYSTEM AND METHOD 审中-公开
标题翻译：集成的证明流程系统和方法
公开(公告)号：WO2004104871A2
公开(公告)日：2004-12-02
申请号：PCT/US2004/015093
申请日：2004-05-14
申请人： CADENCE DESIGN SYSTEMS, INC. , CHEN, Kuang-Chien , WANG, Bow-Yaw
发明人： CHEN, Kuang-Chien , WANG, Bow-Yaw
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Integrated proof flow methods and apparatuses are discussed. Integrated proof flow refers to attempting both formal verification and nonformal verification. A coverage metric can be changed by both attempting formal verification and by attempting nonformal verification. Some embodiments of the present invention provide proof flow methods that integrate verification and nonformal verification (e.g., bounded verification, multi-point proof, and/or vector-based simulation) to prove one or more properties in a circuit design.
摘要翻译：讨论了集成验证流程的方法和设备。集成证明流程是指尝试正式验证和非形式验证。可以通过尝试正式验证和尝试非正式验证来更改覆盖度量。本发明的一些实施例提供集成验证和非形式验证（例如，有界验证，多点证明和/或基于向量的模拟）以证明电路设计中的一个或多个属性的证明流程方法。

73. 发明申请

WO2004047001A2 METHOD, SYSTEM, AND ARTICLE OF MANUFACTURE FOR IMPLEMENTING METAL-FILL 审中-公开
标题翻译：用于实施金属填充的方法，系统和制造物品
公开(公告)号：WO2004047001A2
公开(公告)日：2004-06-03
申请号：PCT/US2003/036989
申请日：2003-11-19
申请人： CADENCE DESIGN SYSTEMS, INC. , VUONG, Thanh , KAO, William, H. , NOICE, David, C.
发明人： VUONG, Thanh , KAO, William, H. , NOICE, David, C.
IPC分类号： G06K
CPC分类号： G06F17/5068
摘要： Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.
摘要翻译：公开了用于实现用于集成电路的金属填充的单程方法的方法，系统和制品。还公开了用于实现耦合到系留连接的金属填充物的方法，系统和制品。公开的方法包括用于实现具有对应于空白长度的细长形状的金属填充物的方法，系统和制品。还公开了实现与布线方向匹配的金属填充的方面。另一个公开是地点＆amp; 包含集成金属填充机制的路线工具。

74. 发明申请

WO2004025706A2 AUTOMATIC INSERTION OF CLOCKED ELEMENTS INTO AN ELECTRONIC DESIGN TO IMPROVE SYSTEM PERFORMANCE 审中-公开
标题翻译：将时钟元件自动插入电子设计以提高系统性能
公开(公告)号：WO2004025706A2
公开(公告)日：2004-03-25
申请号：PCT/US2003/028932
申请日：2003-09-13
申请人： CADENCE DESIGN SYSTEMS, INC.
发明人： SCHEFFER, Louis, K.
IPC分类号： H01L
CPC分类号： G06F17/5045
摘要： A method of improving a design of an electronic circuit includes generating the design, specifying one or more pipeline locations of the design, modifying the one or more pipeline locations of the design, and communicating the results to a user.
摘要翻译：改进电子电路设计的方法包括生成设计，指定设计的一个或多个流水线位置，修改设计的一个或多个流水线位置，以及将结果传达给用户。

75. 发明申请

WO2004008245A3 METHOD AND SYSTEM FOR CONTEXT-SPECIFIC MASK INSPECTION 审中-公开
公开(公告)号：WO2004008245A3
公开(公告)日：2004-01-22
申请号：PCT/US2003/021995
申请日：2003-07-14
申请人： CADENCE DESIGN SYSTEMS, INC.
发明人： PACK, Robert, C. , SHEFFER, Louis, K.
IPC分类号： G06F7/60
摘要： A method for inspecting lithography masks (108) includes generating integrated circuit design data (102) and using context information from the integrated circuit design data to inspect a mask.

76. 发明申请

WO03100704A2 ASSERTION-BASED TRANSACTION RECORDING 审中-公开
标题翻译：基于约定的交易记录
公开(公告)号：WO03100704A2
公开(公告)日：2003-12-04
申请号：PCT/US0316996
申请日：2003-05-28
申请人： CADENCE DESIGN SYSTEMS INC
发明人： MARSCHNER FRANZ ERICH , LAWRENCE JAMES M , WARD STEPHEN T
IPC分类号： G06F17/50 , G06K
CPC分类号： G06F17/5022
摘要： An assertion based transaction recording method is used to represent a signal-level transaction having a prefix and a suffix as an abstract transaction. The method models the signal-level transaction as an assertion requiring that the transaction suffix must occur following any occurrence of the transaction prefix. A finite-state-machine (FSM) implementation of the assertion records a tentative abstract transaction upon recognizing the first condition of the prefix. If the FSM recognizes that the prefix cannot complete, it cancels, or deletes, the tentative abstract transaction record. The implementation can track multiple tentative abstract transaction records that may co-exist prior to completion of the transaction prefix. Upon recognizing that the transaction prefix corresponding to the start point of the tentative abstract transaction has completed, the tentative abstract transaction record is committed. The FSM implementation of the assertion can then cancel all other outstanding tentative abstract transaction records.
摘要翻译：基于断言的事务记录方法用于表示具有前缀和后缀作为抽象事务的信号级事务。该方法将信号级别事务建模为断言，要求事务后缀必须在事务前缀出现之后发生。断言的有限状态机（FSM）实现在识别前缀的第一个条件时记录一个暂时的抽象事务。如果FSM认识到前缀不能完成，则取消或删除暂定抽象事务记录。该实现可以跟踪在交易前缀完成之前可能共存的多个临时抽象交易记录。一旦认识到与暂定抽象事务的起始点相对应的事务前缀已经完成，则提交临时抽象事务记录。断言的FSM实现可以取消所有其他未完成的暂定抽象交易记录。

77. 发明申请

WO2003077630A3 METHOD AND APPARATUS FOR SYNTHESIS 审中-公开
公开(公告)号：WO2003077630A3
公开(公告)日：2003-09-25
申请号：PCT/US2003/002984
申请日：2003-01-31
申请人： CADENCE DESIGN SYSTEMS, INC. , TEIG, Steven , ASMUS, Hetzel
发明人： TEIG, Steven , ASMUS, Hetzel
IPC分类号： G06F17/50
摘要： A method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function (605), (2) generates a parameter based on this function (610), and (3) stores the sub-network in a storage structure based on the generated parameters (635).

78. 发明申请

WO2003054750A1 SYSTEM AND METHOD FOR PROVIDING BURST LICENSING IN A CIRCUIT SIMULATION ENVIRONMENT 审中-公开
标题翻译：在电路仿真环境中提供爆炸物许可的系统和方法
公开(公告)号：WO2003054750A1
公开(公告)日：2003-07-03
申请号：PCT/US2002/041279
申请日：2002-12-19
申请人： CADENCE DESIGN SYSTEMS, INC.
发明人： FOSTER, Paul, Christopher , BRITTON, James , SEITER, Rich , MAYES, Alan
IPC分类号： G06F17/50
CPC分类号： G06F21/105 , G06F17/50
摘要： A system and method which allows for burst licensing, particularly for use in a circuit design and analysis system in which designers use tools to assist in characterizing and verifying the circuit. Burst licensing is used to provide licenses (166, 174, 182)on an ‘as and when required’ basis to allow system users or customers to carry out massive parallelism of the simulation tasks when run from selected tools. When the system receives a request to start a task (162,170,178), the system checks-out a burst license (166,174,182) for use in processing the task and assigns the license to a particular CPU. The task is then performed at that CPU (154,156,158), and once completed the burst license is returned to the license pool (160).
摘要翻译：允许突发许可的系统和方法，特别是用于设计者使用工具来协助表征和验证电路的电路设计和分析系统。突发许可证用于在“根据需要”的基础上提供许可证（166,174,182），以允许系统用户或客户在从所选工具运行时执行仿真任务的大规模并行。当系统接收到启动任务的请求（162,170,178）时，系统检查突发许可证（166,174,182）以用于处理任务并将许可分配给特定的CPU。然后在该CPU（154,156,158）执行该任务，并且一旦完成，则将突发许可证返回给许可证池（160）。

79. 发明申请

WO2003050724A3 TIMING MODEL EXTRACTION BY TIMING GRAPH REDUCTION 审中-公开
公开(公告)号：WO2003050724A3
公开(公告)日：2003-06-19
申请号：PCT/US2002/038799
申请日：2002-12-06
申请人： CADENCE DESIGN SYSTEMS, INC.
发明人： MOON, Cho, Woo , KRIPLANI, Harish , BELKHALE, Krishna, Prasad
IPC分类号： G06F17/50
摘要： Disclosed is a method and system for extracting a timing model. One disclosed approach to extract a timing model is by reducing the timing graph. Original timing behavior is preserved in the timing model including arrival times, slew times, timing violations and even latch time borrowing that is independent of clock waveforms. Also, original timing constraints can be captured in the model and be applied automatically when the model is used. Anchor points are automatically identified and retained to obtain a model that is smaller than the original netlist.

80. 发明申请

WO0125974A3 METHOD AND SYSTEM FOR GENERIC INFERENCE OF SEQUENTIAL ELEMENTS 审中-公开
标题翻译：一般来说，序列元素的方法和系统
公开(公告)号：WO0125974A3
公开(公告)日：2003-04-17
申请号：PCT/US0027219
申请日：2000-10-02
申请人： CADENCE DESIGN SYSTEMS INC
发明人： PEDENON ARNAUD
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945
摘要： A method for inferring a requested data input function of a sequential cell from a library of candidate cells, wherein the requested cell and the candidate cell are expressed as polynoms and then divided. The method generates polynomial expressions of the inhibition, transformation and inference steps necessary to convert the candidate cell into the requested cell. The use of polynomial expression and division greatly reduces the number of rules necessary to accommodate the varying combinations of requested cell and candidate cell functions.
摘要翻译：一种用于从候选小区的库推断顺序单元的请求数据输入功能的方法，其中所请求的单元和候选单元被表示为多项式，然后被划分。该方法生成将候选小区转换为所请求的小区所需的抑制，转换和推理步骤的多项式表达式。使用多项式表达式和除法大大减少了适应所请求的单元和候选单元函数的变化组合所必需的规则数量。

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