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71. 发明申请

WO2006071385A2 DATA FILE STORING MULTIPLE DATA TYPES WITH CONTROLLED DATA ACCESS 审中-公开
标题翻译：数据文件存储具有受控数据访问的多种数据类型
公开(公告)号：WO2006071385A2
公开(公告)日：2006-07-06
申请号：PCT/US2005/041419
申请日：2005-11-15
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, C.,John , SCHULTE, Michael, J.
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, C.,John , SCHULTE, Michael, J.
IPC分类号： G06F15/00
CPC分类号： G06F9/30112
摘要： A method and apparatus for efficiently storing multiple data types in a computer’s register or data file. A single data file can store data with a variety of sizes and number formats, including integers, fractions, and mixed numbers. The register file is partitioned into fields, such that only the relevant portions of the register file are read or written.
摘要翻译：一种用于在计算机的寄存器或数据文件中有效地存储多种数据类型的方法和装置。单个数据文件可以存储具有各种大小和数字格式的数据，包括整数，分数和混合数。寄存器文件被分割成字段，使得仅读取或写入寄存器文件的相关部分。

72. 发明申请

WO2006036405A2 METHOD OF DETERMINING AN ACQUISITION INDICATOR BIT IN A COMMUNICATION SYSTEM 审中-公开
标题翻译：在通信系统中确定采集指示符位的方法
公开(公告)号：WO2006036405A2
公开(公告)日：2006-04-06
申请号：PCT/US2005/030195
申请日：2005-08-25
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： SANDBRIDGE TECHNOLOGIES, INC. , CHUN, Joon-Hwa
IPC分类号： H04L12/56
CPC分类号： H04B1/70755 , H04B1/7075
摘要： A method of determining an acquisition indicator bit AI s , at a receiver in a communication system which includes receiving multiplexed acquisition indicator bits y = B x AI + n, where B is the signature matrix known at both base station and UE, AI is all the acquisition indicator bits and n represents noise. Next, an estimated value of the acquisition indicator bit AÎ MMSE (s) as a function of formula (I) is calculated, where B T (s,.) is the s -th row vector of the transposed matrix B T for acquisition indicator bit AI s ,. Finally, the acquisition indicator bit AI S is set as follows: AI s. =-1, if AÎ MMSE (s) S =0, if R ≤ AÎ, MMSE SE (s) s =1, if AÎ MMSE (s) ≥ U, where R and U are decision thresholds.
摘要翻译：一种确定采集指示符位AI

73. 发明申请

WO2004103056A3 PROCESSOR REDUCTION UNIT FOR ACCUMULATION OF MULTIPLE OPERANDS WITH OR WITHOUT SATURATION 审中-公开
标题翻译：用于累积或不饱和的多个操作的处理器减少单元
公开(公告)号：WO2004103056A3
公开(公告)日：2005-12-29
申请号：PCT/US2004014257
申请日：2004-05-07
申请人： SANDBRIDGE TECHNOLOGIES INC
发明人： SCHULTE MICHAEL J , BALZOLA PABLO I , HOKENEK ERDEM , GLOSSNER JOHN C
IPC分类号： G06F7/00 , G06F7/38 , G06F7/544 , G06F9/302 , G06F9/38
CPC分类号： G06F9/3885 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30101 , G06F9/3851
摘要： A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.
摘要翻译：具有减少单元的处理器，其将m个输入操作数加上累加器值相加，并且可以在每次添加之后饱和选项或围绕每次添加的结果进行包围。缩小单元还允许通过简单地反转输入操作数的位并将多个还原加法器中的每一个设置为一个，从累加器值中减去m个输入操作数。还原单元可以与m个并行乘法器一起使用，以便通过饱和或环绕运算来快速执行点积和其他向量运算。

74. 发明申请

WO2005101221A1 MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD 审中-公开
标题翻译：多通道加工器，每个螺纹多个并流管道
公开(公告)号：WO2005101221A1
公开(公告)日：2005-10-27
申请号：PCT/US2005/011614
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J. , GLOSSNER, C., John
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J. , GLOSSNER, C., John
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/30036 , G06F9/30101 , G06F9/30123 , G06F9/3893
摘要： A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.
摘要翻译：多线程处理器包括多个硬件线程单元，耦合到用于解码从其接收的指令的线程单元的指令解码器，以及用于执行解码指令的多个执行单元。多线程处理器被配置为用于控制与相应硬件线程单元相关联的线程的指令发布序列。在给定的处理器时钟周期中，仅允许指定的一个线程发出一个或多个指令，但是允许发出指令的指定线程根据指令发布顺序在多个时钟周期内变化。这些指令以允许至少给定的一个线程支持多个并行指令流水线的方式流水线化。

75. 发明申请

WO2005086675A2 ARITHMETIC CIRCUIT WITH BALANCED LOGIC LEVELS FOR LOW-POWER OPERATION 审中-公开
标题翻译：具有平衡逻辑电平的低功耗操作的算术电路
公开(公告)号：WO2005086675A2
公开(公告)日：2005-09-22
申请号：PCT/US2005/007021
申请日：2005-03-04
申请人： SANDBRIDGE TECHNOLOGIES, INC. , CHIRCA, Kai , GLOSSNER, C., John
发明人： CHIRCA, Kai , GLOSSNER, C., John
IPC分类号： G06F7/50
CPC分类号： G06F7/506
摘要： An adder circuit comprising a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least give one of the adder stages are substantially balanced in terms of a number of gate delays experienced by said signals within said adder circuit in arriving at their respective inputs of the carry out computation element. Advantageously, this provides significant reductions in both dynamic switching power and short circuit power in the adder circuit.
摘要翻译：一种加法器电路，包括串联互连的多个加法器级，除了最后加法级之外的每个加法级的进位被耦合到后一个加法级的进位。至少给出加法器级中的一个，进位，产生和传播施加到进位计算元件的相应输入端的信号在所述加法器电路中达到其相应输入时所经历的门数延迟的数目基本平衡的进位计算元素。有利地，这提供了加法器电路中的动态开关功率和短路功率的显着降低。

76. 发明申请

WO2005010746A1 ARITHMETIC UNIT FOR ADDITION OR SUBTRACTION WITH PRELIMINARY SATURATION DETECTION 审中-公开
标题翻译：用于添加或减去初步饱和度检测的算术单元
公开(公告)号：WO2005010746A1
公开(公告)日：2005-02-03
申请号：PCT/US2004/023431
申请日：2004-07-21
申请人： SANDBRIDGE TECHNOLOGIES, INC. , SCHULTE, Michael, J. , HOKENEK, Erdem , BALZOLA, Pablo, I. , GLOSSNER, John, C.
发明人： SCHULTE, Michael, J. , HOKENEK, Erdem , BALZOLA, Pablo, I. , GLOSSNER, John, C.
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/49921
摘要： An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry. The saturation circuitry has inputs coupled to corresponding outputs of the first arithmetic circuitry and the selection circuitry, and is configured to generate a result of the arithmetic operation.
摘要翻译：一种用于对至少第一和第二输入操作数执行算术运算的算术单元，每个输入操作数可分为第一部分和第二部分，例如各自不太重要和更重要的部分。算术单元包括第一运算电路，第二运算电路，选择电路和饱和电路。可以包括进位传播加法器的第一运算电路处理输入操作数的第一部分以产生至少一个临时和和进位输出。可以包括双加法器和初步饱和检测器的第二运算电路处理输入操作数的第二部分以产生一个或多个临时和和多个饱和标志。选择电路被配置为基于第一运算电路的进位输出来选择第二运算电路的一个或多个输出。饱和电路具有耦合到第一算术电路和选择电路的对应输出的输入，并且被配置为产生算术运算的结果。

77. 发明申请

WO2004095726A1 AM RECEIVER AND DEMODULATOR 审中-公开
标题翻译：接收器和解调器
公开(公告)号：WO2004095726A1
公开(公告)日：2004-11-04
申请号：PCT/US2004/006866
申请日：2004-03-08
申请人： SANDBRIDGE TECHNOLOGIES, Inc.
发明人： IANCU, Daniel
IPC分类号： H04B1/28
CPC分类号： H04B1/0021 , H03G3/3036 , H03G3/3052 , H04B1/0003 , H04B1/28
摘要： An amplitude modulation receiver including an antenna (10) for receiving a signal (1) and an input filter (12) connected to the antenna. A variable gain amplifier (16) is connected to the input filter and is responsive to a gain control signal. An A/D converter is connected to the variable gain amplifier and is responsive to a sampling signal and provides a sampled digital signal. A D/A converter (22) receives a demodulated signal and provides an analog output signal. A controller (20) receives and demodulates the sampled digital signal from the A/D converter, generates the gain control signal for the variable gain amplifier, generates the sampling signal for the A/D converter, and provides the demodulated signal to the D/A converter. The demodulation and generation of the gain control signal and the sampling signal are performed in software.
摘要翻译：一种幅度调制接收机，包括用于接收信号的天线（10）和连接到天线的输入滤波器（12）。可变增益放大器（16）连接到输入滤波器并响应于增益控制信号。 A / D转换器连接到可变增益放大器，并响应采样信号并提供采样的数字信号。 D / A转换器（22）接收解调信号并提供模拟输出信号。控制器（20）接收并解调来自A / D转换器的采样数字信号，产生用于可变增益放大器的增益控制信号，产生用于A / D转换器的采样信号，并将解调信号提供给D / A转换器。增益控制信号和采样信号的解调和产生是以软件进行的。

78. 发明申请

WO2004034340A2 METHOD AND APPARATUS FOR TOKEN TRIGGERED MULTITHREADING 审中-公开
标题翻译：用于手动多功能的方法和装置
公开(公告)号：WO2004034340A2
公开(公告)日：2004-04-22
申请号：PCT/US2003/031905
申请日：2003-10-09
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, John, C.
IPC分类号： G07F
CPC分类号： G06F9/3867 , G06F9/3851
摘要： Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and utilizing the stored value to control the instruction issuance sequence. For example, each of a plurality of hardware thread units of the multithreaded processor may include a corresponding local register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions. A global register arrangement may also or alternatively be used. The processor may be configured so as to permit the instruction issuance sequence to correspond to an arbitrary alternating even-odd sequence of threads, without introducing blocking conditions leading to thread stalls.
摘要翻译：公开了一种用于多线程处理器中令牌触发多线程的技术。多线程处理器的多个线程的指令发布序列通过与每个线程相关联来控制，该至少一个寄存器存储标识下一个线程的值以允许发出一个或多个指令，并且利用存储的值控制指令发布顺序。例如，多线程处理器的多个硬件线程单元中的每一个可以包括可由该硬件线程单元更新的对应的本地寄存器，其中给定的一个硬件线程单元的本地寄存器存储标识下一个线程的值允许在给定的硬件线程单元发出一个或多个指令之后发出一个或多个指令。还可以或替代地使用全局寄存器布置。处理器可以被配置为允许指令发布序列对应于任意交替偶数奇数序列的线程，而不引入导致线程停顿的阻塞条件。

79. 发明申请

WO2004034209A2 METHOD AND APPARATUS FOR REGISTER FILE PORT REDUCTION IN A MULTITHREADED PROCESSOR 审中-公开
标题翻译：用于多线程处理器中的寄存器文件端口减少的方法和装置
公开(公告)号：WO2004034209A2
公开(公告)日：2004-04-22
申请号：PCT/US0331904
申请日：2003-10-09
申请人： SANDBRIDGE TECHNOLOGIES INC
发明人： HOKENEK ERDEM , MOUDGILL MAYAN , GLOSSNER C JOHN
IPC分类号： G06F20060101 , G06F9/00 , G06F9/30 , G06F9/38 , G06F9/54 , G06F12/02 , G06F13/16 , G06F15/167 , G06F
CPC分类号： G06F9/30123 , G06F9/3851
摘要： Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated register file to be accessed by the corresponding processor thread. In an illustrative embodiment, the register file is divided into even and odd portions, with a least significant bit or other portion of the thread identifier being used to select either the even or the odd portion for use by a given processor thread. The thread-based register file selection may be utilized in conjunction with token triggered threading and instruction pipelining. Advantageously, the invention reduces register file port requirements and thus processor power consumption, while maintaining desired levels of concurrency.
摘要翻译：公开了通过多线程处理器进行基于线程的寄存器文件访问的技术。多线程处理器确定与特定处理器线程相关联的线程标识符，并且利用线程标识符的至少一部分来选择要由相应处理器线程访问的相关联寄存器文件的特定部分。在说明性实施例中，寄存器文件被分成偶数部分和奇数部分，线程标识符的最低有效位或其他部分被用于选择给定处理器线程使用的偶数部分或奇数部分。基于线程的寄存器文件选择可以与令牌触发线程和指令流水线结合使用。有利的是，本发明减少了寄存器文件端口要求，从而减少了处理器功耗，同时保持了期望的并发水平。

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