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61. 发明申请

WO2002080350A1 POWER OSCILLATOR FOR CONTROL OF WAVESHAPE AND AMPLITUDE 审中-公开
标题翻译：用于控制波形和振幅的功率振荡器
公开(公告)号：WO2002080350A1
公开(公告)日：2002-10-10
申请号：PCT/US2002/004697
申请日：2002-02-19
申请人： CUBIC CORPORATION , BUSCH-SORENSEN, Thomas
发明人： BUSCH-SORENSEN, Thomas
IPC分类号： H03B28/00
CPC分类号： G06K19/0701 , G06K7/0008 , H03B28/00 , H03C1/36 , H03C1/62 , H03K5/14 , H03K7/02
摘要： An RF power oscillator for contactless card antennas shapes a carrier signal at the operating frequency utilizing a delay circuit having a number of taps for delaying the carrier signal by different lengths of time. The delayed signals are input into a buffer and output through resistors to a node coupled to the antenna. The resulting waveform for a square wave input signal, and equal-length delay taps, is a trapezoidal wave output. Any input wave form can be shaped in a variety of ways depending upon the combinations of delay taps used. Since the buffer drivers for each delayed wave switch state at slightly different times, the amplitude and bandwidth of emitted electromagnetic interference (EMI) is reduced for the transmission circuit.
摘要翻译：用于非接触卡天线的RF功率振荡器利用具有多个抽头的延迟电路以工作频率对载波信号进行整形，以将载波信号延迟不同的时间长度。延迟信号被输入缓冲器并通过电阻器输出到耦合到天线的节点。对于方波输入信号和等长延迟抽头的结果波形是梯形波输出。任何输入波形可以根据所使用的延迟抽头的组合以各种方式成形。由于每个延迟波开关的缓冲驱动器在稍微不同的时间状态，所以发射电路的发射电磁干扰（EMI）的幅度和带宽减小。

62. 发明申请

WO00055973A3 DIRECT DIGITAL FREQUENCY SYNTHESIS ENABLING SPUR ELIMINATION 审中-公开
标题翻译：直接数字频率综合法消除某些寄生虫
公开(公告)号：WO00055973A3
公开(公告)日：2000-12-28
申请号：PCT/US2000/006757
申请日：2000-03-16
IPC分类号： H03B28/00 , H03C3/09 , H03L7/08 , H03L7/085 , H03L7/089 , H03L7/18 , H03B21/00 , H03L7/16
CPC分类号： H03C3/0991 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/085 , H03L7/0891 , H03L7/1806
摘要： The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a "difference engine" is provided that produces a digital signal representing the frequency error between a numeric frequency and an analog frequency. The frequency error may be digitally integrated to produce a digital signal representing the phase error. The difference engine may be incorporated into a PLL, where the analog frequency is that of an output signal of a VCO of the PLL. Direct modulation of the PLL output signal may be performed numerically. By further providing an auxiliary modulation path and performing calibration between the direction modulation path and the auxiliary modulation path, modulation characteristics may be separated from loop bandwidth constraints. In particular, the loop bandwidth of the PLL may be made so low as to reduce spurs (usually associated with DDS techniques) to an arbitrarily low level. A loop filter of the PLL may be realized in digital form. Using a digital loop filter would ordinarily require use of a high-resolution DAC. Various techniques are described for reducing the resolution requirements of the DAC.
摘要翻译：本发明一般涉及用于产生精确调制的清洁波的改进方法，至少部分地归功于数字技术。根据本发明的一个方面，使用“对比度引擎”来产生代表数字频率和模拟频率之间的频率误差的数字信号。该频率误差可以数字积分以产生代表相位误差的数字信号。对比度引擎可以集成在PLL环路中，其中模拟频率是PLL的压控振荡器（VCO）的输出信号的频率。 PLL回路的输出信号的直接调制可以用数字来完成。通过使用辅助调制路径并在感测调制路径和辅助调制路径之间执行校准，可以克服环路相对于调制特性的带宽限制。具体而言，可以将PLL的带宽缩小到可以将噪声（通常与直接数字合成（DDS）技术相关联）降低到任意低水平的程度。 PLL回路的环路滤波器可以以数字形式实现。使用数字环路滤波器通常需要使用高分辨率DAC。本发明涉及用于降低分类器的分辨率要求的各种技术。

63. 发明申请

WO00008792A2 SYSTEM AND METHOD EMPLOYING A REDUCED NCO LOOKUP TABLE 审中-公开
标题翻译：使用减少的NCO查询表的系统和方法
公开(公告)号：WO00008792A2
公开(公告)日：2000-02-17
申请号：PCT/SE1999/001319
申请日：1999-07-27
IPC分类号： G06F17/10 , G06F17/14 , H03B21/02 , H03B28/00 , H04L27/18 , H04L27/26 , H04L , G06F , H03B , H03L
CPC分类号： H03B21/02 , H04L27/2657 , H04L27/2684
摘要： A system and method for reducing the computational complexity of the calculations performed by a Numerically Controlled Oscillator (NCO) (340). Through exploitation of mathematical symmetries and other techniques, the size of a lookup table (355) of sinusoidal values employed by the NCO (340) to approximate sinusoids may be reduced by the combination of different frequency shifts (510, 520).
摘要翻译：一种用于降低由数控振荡器（NCO）执行的计算的计算复杂度的系统和方法（340）。通过利用数学对称性和其他技术，可以通过不同频移（510,520）的组合来减少由NCO（340）用于近似正弦曲线的正弦值的查找表（355）的大小。

64. 发明申请

WO99038252A1 FREQUENCY SYNTHESIS CIRCUIT TUNED BY DIGITAL WORDS 审中-公开
标题翻译：数字频段调谐频率合成电路
公开(公告)号：WO99038252A1
公开(公告)日：1999-07-29
申请号：PCT/US1999/000873
申请日：1999-01-14
IPC分类号： H03B21/00 , H03B28/00 , H03L7/06 , H03L7/081 , H03L7/16 , H03L7/18
CPC分类号： H03L7/0812 , H03B28/00 , H03L7/16
摘要： A direct digital frequency synthesizer featuring a modulo accumulator (17; 117) addressing a multiplexer (33; 133). The multiplexer receives a series of delay signals generated from digital circuits (41-45; 141-153). The delay signals establish the phase of a reference oscillator (37; 137). The number of units of delay are sufficient to resolve expected jitter. The accumulator is a digital counter which increments by only a single digit for each count, such as a Gray code counter. In one embodiment, the delay signals are generated by a charge pump (43; Fig. 5) feeding individual logic circuits (41; Figs. 3-4) driving integrated capacitors in a loop. Feedback to the charge pump establishes that the total delay will subdivide a single clock cycle of the reference clock. In a second embodiment, a single shifter or several shifters (151; 153), with output in phase reversal relation (145), subdivide a single clock cycle. A clock multiplier (141) and divider (147) are used to assure the synchronism of each clock cycle with the total number of units of delay. The output (33; 155) of the multiplexer (33; 133) is the reference oscillator signal, adjusted by the phase delay, forming a synthesized output frequency.
摘要翻译：一种直接数字频率合成器，其特征在于寻址多路复用器（33; 133）的模累加器（17; 117）。多路复用器接收从数字电路（41-45; 141-153）产生的一系列延迟信号。延迟信号建立参考振荡器（37; 137）的相位。延迟单位的数量足以解决预期的抖动。累加器是一个数字计数器，每个计数器只增加一个数字，例如格雷码计数器。在一个实施例中，延迟信号由馈送各个逻辑电路（41;图3-4）的电荷泵（43;图5）产生，该循环驱动集成电容器。对电荷泵的反馈确定总延迟将细分参考时钟的单个时钟周期。在第二实施例中，具有输出相位反转关系（145）的单个移位器或多个移位器（151; 153）细分单个时钟周期。使用时钟乘法器（141）和分频器（147）来确保每个时钟周期与延迟单元总数的同步。多路复用器（33; 133）的输出（33; 155）是由相位延迟调整的参考振荡器信号，形成合成输出频率。

65. 发明申请

WO99014848A1 METHOD AND ARRANGEMENT IN A DIGITAL OSCILLATOR 审中-公开
标题翻译：数字振荡器中的方法和布置
公开(公告)号：WO99014848A1
公开(公告)日：1999-03-25
申请号：PCT/SE1998/001291
申请日：1998-06-30
IPC分类号： G06F1/02 , H03B27/00 , H03B28/00
CPC分类号： H03B27/00 , G06F1/022 , H03B28/00
摘要： The present invention is related to a digital oscillator (400) for use in a radio receiver (110). The oscillator comprises a signal generator (401), generating a digital sinusoidal signal (S43). The digital sinusoidal signal (S43) is fed into phase shifting means (402) being separate from the signal generator (401). The phase shifting means (402) derives from the digital sinusoidal signal (S43) a first pair of digital sinusoidal signals (S44, S45) having a phase difference corresponding to at least one sample step. The first pair of digital sinusoidal signals (S44, S45) is fed into orthogonalization means (403) which produces a pair of orthogonal digital sinusoidal signal (S41, S42) by forming linear combinations of the first pair of digital sinusoidal signals (S44, S45).
摘要翻译：本发明涉及一种用于无线电接收机（110）的数字振荡器（400）。振荡器包括产生数字正弦信号的信号发生器（401）（S43）。数字正弦信号（S43）馈送到与信号发生器（401）分开的相移装置（402）中。相移装置（402）从数字正弦信号（S43）导出具有对应于至少一个采样步骤的相位差的第一对数字正弦信号（S44，S45）。第一对数字正弦信号（S44，S45）被馈送到通过形成第一对数字正弦信号的线性组合（S44，S45）产生一对正交数字正弦信号（S41，S42）的正交化装置（403））。

66. 发明申请

WO1997024797A1 DIGITAL FREQUENCY GENERATOR 审中-公开
标题翻译：数字频率发生器
公开(公告)号：WO1997024797A1
公开(公告)日：1997-07-10
申请号：PCT/GB1996003240
申请日：1996-12-27
申请人： SHINE, Thomas, Adam , SHINE, Ian, Basil
IPC分类号： H03B28/00
CPC分类号： A61M5/172 , H02P8/14 , H03B28/00
摘要： In a method of generating a clock signal having a desired frequency, a pulse is generated each time a stored accumulator value ( tank ) is found to be greater than or equal to a stored ( trigger ) value. In a first loop (10), the stored accumulator value ( tank ) is iteratively incremented by a first iterative value ( r ) until the stored accumulator value is greater than or equal to the stored trigger value and subsequently in a second loop (11) the stored accumulator value ( tank ) is decremented by a second iterative value until the stored accumulator value is less than the stored trigger value. During each iteration of the first loop (10), a current frequency of the clock signal is compared to a desired frequency value and if the two values are different, the first iterative value ( r ) is corrected at a predetermined rate ( accRate ) over one of more subsequent iterations until the frequency of the generator clock signal corresponds to the detected value of the desired frequency. In a preferred example, the number of iterations needed to change the first iterative value ( r ) is determined by a stored accumulator value which is added to an accelerator-accumulator ( AccTank ) for each iteration that the first iterative value and the desired frequency are not exactly equal.
摘要翻译：在产生具有期望频率的时钟信号的方法中，每当发现所存储的累加器值（u> tank）大于或等于存储的（触发器< / u>）值。在第一循环（10）中，所存储的累加器值（ tank）被迭代地增加第一迭代值（u），直到存储的累加器值大于或等于到存储的触发器值，随后在第二循环（11）中，存储的累加器值（ tank）被递减第二迭代值，直到存储的累加器值小于存储的触发器值。在第一循环（10）的每次迭代期间，将时钟信号的当前频率与期望频率值进行比较，并且如果两个值不同，则第一迭代值（ui）被校正为直到发生器时钟信号的频率对应于所需频率的检测值为止，在更多的后续迭代中的一个以上的预定速率（“acc”）。在优选示例中，改变第一迭代值（ r ）所需的迭代次数由存储的累加器值确定，该累加器值被加到加速器累加器）对于每次迭代，第一迭代值和期望频率不是完全相等的。

67. 发明申请

WO2021116911A1 SINGLE LAYER LC OSCILLATOR 审中-公开
公开(公告)号：WO2021116911A1
公开(公告)日：2021-06-17
申请号：PCT/IB2020/061652
申请日：2020-12-08
申请人： WILIOT, LTD.
发明人： YEHEZKELY, Alon , ELBOIM, Yaron
IPC分类号： H01L23/64 , H03L1/02 , H03B28/00
摘要： An LC oscillator is provided. The LC oscillator includes a single layer inductor disposed within a single layer inlay, wherein the single layer inductor is configured in a spiral pattern within the layer of the inlay, wherein an integrated circuit is mounted on the single layer inlay; and a capacitor included in the integrated circuit, wherein the capacitor is connected to the single layer inductor.

68. 发明申请

WO2021059297A1 METHOD AND SYSTEM FOR GENERATING A WAVEFORM IN A COMMUNICATION NETWORK 审中-公开
公开(公告)号：WO2021059297A1
公开(公告)日：2021-04-01
申请号：PCT/IN2020/050820
申请日：2020-09-25
申请人： WISIG NETWORKS PRIVATE LIMITED , INDIAN INSTITUTE OF TECHNOLOGY HYDERABAD
发明人： AMURU, Saidhiraj , MAKANDAR, Sibgath Ali Khan , KUCHI, Kiran Kumar
IPC分类号： H04B7/06 , H03B28/00 , G06F1/03
摘要： Embodiments of the present disclosure relate to system and method for generating a waveform in a communication network is disclosed. The method comprises determining precoder information using one of an indication from a base station and predetermined parameters corresponding to precoding. The predetermined parameters are one of coefficients of the precoding filter, and flatness requirement of the precoding filter. Also, the method comprises generating a sequence of output modulation symbols, wherein each output modulation symbol is obtained using a block of input data symbols and a lookup table. The lookup table is a function of the precoder information and pre-determined modulation information. Next, the sequence of output modulation symbols is transformed using Discrete Fourier Transform to generate transformed output modulation symbols. Thereafter, mapping the transformed output modulation symbols using a plurality of subcarriers to generate a sub-carrier mapped symbols and processing the sub-carrier mapped symbols to generate a waveform.

69. 发明申请

WO2019043814A1 三角関数近似装置、三角関数近似方法、および三角関数近似プログラム审中-公开
公开(公告)号：WO2019043814A1
公开(公告)日：2019-03-07
申请号：PCT/JP2017/031066
申请日：2017-08-30
申请人：三菱電機株式会社
发明人：西辻　崇
IPC分类号： H03B28/00
摘要：主生成部（１１）が、位相信号（５１）を用いて理想関数と同調する第１鋸波信号（５０１）を生成する。調整部（１２１）が、位相信号（５１）を定数倍するとともに定数加算した調整信号（６０４）を生成する。副生成部（１２２）が、調整信号（６０４）を用いて、位相と周波数とが、第１鋸波信号（５０１）から生成された近似三角波信号との誤差を表した誤差関数を相殺する誤差補正信号（６０３）と同じ第２三角波信号（６０２）を生成する。第２補正部（１２３）が、第２三角波信号（６０２）の波形の値域を調整し、誤差補正信号（６０３）を生成する。加算部（１１３）が、第１鋸波信号（５０１）と誤差補正信号（６０３）とを加算し、補正鋸波信号（５０１ａ）を生成する。近似信号生成部（１１４）が、補正鋸波信号（５０１ａ）を用いて、近似信号（５２）を生成する。

70. 发明申请

WO2018134838A1 SYSTEM AND METHOD FOR GENERATING SPREADED SEQUENCE WITH LOW PEAK-TO-AVERAGE POWER RATIO (PAPR) WAVEFORM 审中-公开
公开(公告)号：WO2018134838A1
公开(公告)日：2018-07-26
申请号：PCT/IN2017/050589
申请日：2017-12-12
申请人： WISIG NETWORKS PRIVATE LIMITED
发明人： KUCHI, Kiran Kumar
IPC分类号： H04B1/69 , H03B28/00 , H04L27/00
摘要： Embodiments of the present disclosure relate to a method and system to generate a waveform in a communication network. The transmitter receives an input data and transmit a generated waveform to another communication system. The input data is spread with a spread code to generate a spread data and rotated using a constellation rotation operation to produce a rotated data. The rotated data is then precoded using precoding filter to produce a precoded data, and transformed into DFT output data using DFT operation. The DFT output data is then mapped with subcarriers to generate the sub-carrier mapped DFT data and modulated using Orthogonal Frequency Division Multiplexing (OFDM) modulation to generate the waveform with low PAPR.

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