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61. 发明申请

WO2009128921A2 METHOD AND APPARATUS FOR PRODUCING A METASTABLE FLIP FLOP 审中-公开
标题翻译：用于生产易碎片的方法和装置
公开(公告)号：WO2009128921A2
公开(公告)日：2009-10-22
申请号：PCT/US2009/002358
申请日：2009-04-15
申请人： VNS PORTFOLIO LLC , MOORE, Charles, H.
发明人： MOORE, Charles, H.
IPC分类号： G06F15/16 , H03K3/09 , H04L7/00 , G06F13/42
CPC分类号： G11C5/025 , G11C5/02 , G11C8/14 , Y10T29/49002
摘要： The method includes predetermining an output enable time period by measuring the maximum settling time when a signal is read during a transition from 0 to 1 or vice versa, and multiplying the maximum settling time by a safety factor 2.5, to set an output enable time period; reading and latching an input value; and transmitting the latched value onward after the predetermined output enable time period. An embodiment of the apparatus 10 includes two inverters 12, 14 and two pass gates 16, 18 and connected to a line 20 at its input. The pass gates 16, 18 are connected in a multiplexer configuration. A third pass gate 30 for connecting line 32, carrying the (inverted) output B of the metalatch, to further circuit portions, according to a 2-bit output enable signal applied to control lines 34, 36 respectively. In alternate embodiments, other logic circuit portions already provided can perform the function of pass gate 30.
摘要翻译：该方法包括通过测量在从0到1的转变期间读取信号时的最大建立时间来预定输出使能时间段，反之亦然，并将最大建立时间乘以安全系数2.5，以设置输出使能时间段 ; 读取和锁定输入值; 并且在预定输出使能时间段之后向前发送锁存值。设备10的实施例包括两个反相器12,14和两个传递门16,18，并在其输入处连接到线路20。通路16,18以多路复用器配置连接。根据施加到控制线34,36的2位输出使能信号，连接线32的第三通路门30，其承载金属线的（反相）输出B以进一步电路部分。在替代实施例中，已经提供的其它逻辑电路部分可以执行通路门30的功能。

62. 发明申请

WO2008124503A1 MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE 审中-公开
标题翻译：包括缓冲器器件和集成电路存储器件的存储器系统拓扑
公开(公告)号：WO2008124503A1
公开(公告)日：2008-10-16
申请号：PCT/US2008/059268
申请日：2008-04-03
申请人： RAMBUS INCORPORATED , TSERN, Ely , SHAEFFER, Ian , HAMPEL, Craig
发明人： TSERN, Ely , SHAEFFER, Ian , HAMPEL, Craig
IPC分类号： G11C5/06 , G11C7/10 , G11C5/00
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/4027 , G06F13/4068 , G11C5/025 , G11C5/04 , G11C5/06 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
摘要翻译：除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点对点链路）信号路径提供数据，所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

63. 发明申请

WO2008076790A3 MULTI-DIE MEMORY DEVICE 审中-公开
标题翻译：多重记忆体装置
公开(公告)号：WO2008076790A3
公开(公告)日：2008-09-04
申请号：PCT/US2007087359
申请日：2007-12-13
申请人： RAMBUS INC , BEST SCOTT , LI MING
发明人： BEST SCOTT , LI MING
IPC分类号： G11C5/02
CPC分类号： G11C11/4093 , G11C5/02 , G11C5/025 , G11C5/04 , G11C11/4096 , H01L23/481 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06541 , H01L2225/06558 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/14 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/0401
摘要： An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission.
摘要翻译：集成电路（IC）封装包括接口管芯和单独的存储管芯。接口管芯具有用于从外部存储器控制器接收存储器访问命令的同步接口，并且具有多个无时钟存储器控制接口以输出对应于存储器访问命令的行和列控制信号。存储管芯具有多个可独立访问的存储阵列和对应的访问控制接口以接收来自无时钟存储器控制接口的行和列控制信号，每个访问控制接口包括数据输出电路以输出对应于给出时分复用传输中的一个存储器访问命令。

64. 发明申请

WO2005112035A2 NONVOLATILE MEMORY ARRAY ORGANIZATION AND USAGE 审中-公开
标题翻译：非易失性存储器阵列组织和使用
公开(公告)号：WO2005112035A2
公开(公告)日：2005-11-24
申请号：PCT/US2005/015883
申请日：2005-05-06
申请人： HALO LSI, INC. , OGURA, seiki , OGURA, Tomoko , PARK, Ki-Tae , OGURA, Nori , SATOH, Kimihiro , SAITO, Tomoya
发明人： OGURA, seiki , OGURA, Tomoko , PARK, Ki-Tae , OGURA, Nori , SATOH, Kimihiro , SAITO, Tomoya
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C5/025 , G11C16/16 , G11C16/24 , H01L27/115
摘要： A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device comprises a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/page buffer area shared by several UNITS through a bit decode circuit, wherein the diffusion sub bit lines in each of the UNITS are connected to main bit lines which are in turn connected to the sense amplifier/page buffer area, wherein the bit decode circuit selects one diffusion sub bit line column of memory cells in every E columns.
摘要翻译：实现了用于广泛程序操作的非易失性半导体存储器件阵列组织。该装置包括存储单元阵列区域，其中多个C列和R行存储单元包括一个单元，以“扩散位”阵列组织排列，该阵列组织包括沿第一方向运行的R行字线，以及 C列的扩展子位线，以及在相同的第二方向上运行的子控制栅极线的C列以及由多个UNITS通过位解码电路共享的读出放大器/页缓冲区，其中扩散子位每个UNITS中的线路连接到主位线，主位线又连接到读出放大器/页面缓冲区域，其中位解码电路在每个E列中选择存储器单元的一个扩散子位线列。

65. 发明申请

WO2004097838A2 SPEICHER-SCHALTUNGSANORDNUNG UND VERFAHREN ZUR HERSTELLUNG 审中-公开
标题翻译：存储器电路及其制造方法
公开(公告)号：WO2004097838A2
公开(公告)日：2004-11-11
申请号：PCT/EP2004/050322
申请日：2004-03-17
申请人： INFINEON TECHNOLOGIES AG , GRUBER, Wolfgang , KAKOSCHKE, Ronald , SCHWEIZER, Thomas , WEGERTSEDER, Dominik
发明人： GRUBER, Wolfgang , KAKOSCHKE, Ronald , SCHWEIZER, Thomas , WEGERTSEDER, Dominik
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： Erläutert wird eine Speicher-Schaltungsanordnung (10), bei der sich die Teile des Speichers auf zwei verschiedenen Substraten befinden. Auf dem einen Substrat befindet sich unter anderem ein Speicherzellenfeld (16). Auf dem anderen Substrat befindet sich unter anderem eine Steuerschaltung (38). Durch die geschickte Aufteilung des Speichers lässt sich der Aufwand bei der Herstellung erheblich verringern.
摘要翻译：中描述了一种存储电路装置（10），其中，所述存储器的所述部分位于两个不同的衬底。是，除其他外，在一个衬底上的存储单元阵列（16）。是，除其他外，在另一方的基板上的控制电路（38）。存储器的巧妙划分，在生产费用可以显著降低。

66. 发明申请

WO2003010746A1 DEVICE COMPRISING AN ARRAY OF PIXELS ALLOWING STORAGE OF DATA 审中-公开
标题翻译：包含允许存储数据的像素阵列的设备
公开(公告)号：WO2003010746A1
公开(公告)日：2003-02-06
申请号：PCT/IB2002/002899
申请日：2002-07-25
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： EDWARDS, Martin, J. , AYRES, John, R. A.
IPC分类号： G09G3/36
CPC分类号： G11C8/10 , G09G3/20 , G09G3/3648 , G09G2300/0842 , G11C5/025
摘要： A pixellated device (10), such as a display, has pixel row and column address lines (18,20) for addressing each pixel, thereby providing signal data to each pixel (12) or reading signal data from each pixel. An array of memory cells (22) is provided on the substrate interspersed with the pixel drive circuitry (16), wherein memory address circuitry (24,26,28,30) is provided enabling data to be written to each memory cell and enabling data to be read from each cell (22), independently of the signal data. Each memory cell (22) is thus addressable independently of the pixel data. Thus, the memory cells do not form part of the pixel circuitry, which allows the memory to be used in a flexible manner. For example, the memory may be used for purposes not directly associated with the driving or addressing of the pixels of the device.
摘要翻译：诸如显示器的像素化设备（10）具有用于寻址每个像素的像素行和列地址线（18,20），从而向每个像素（12）提供信号数据或从每个像素读取信号数据。在散布有像素驱动电路（16）的衬底上提供存储单元阵列（22），其中提供存储器地址电路（24,26,28,30），使得能够将数据写入每个存储器单元并使能数据要从每个单元（22）读取，独立于信号数据。因此，每个存储单元（22）可独立于像素数据进行寻址。因此，存储器单元不形成像素电路的一部分，这允许以灵活的方式使用存储器。例如，存储器可以用于与驱动或寻址设备的像素直接相关联的目的。

67. 发明申请

WO0203459A3 HIGH-SPEED LOW-POWER SEMICONDUCTOR MEMORY ARCHITECTURE 审中-公开
标题翻译：高速低功耗半导体存储器架构
公开(公告)号：WO0203459A3
公开(公告)日：2002-05-30
申请号：PCT/US0119896
申请日：2001-06-22
申请人： MOSAIC SYSTEMS INC
发明人： ALEXANIAN SUREN A
IPC分类号： G11C11/41 , G06F7/38 , G11C5/02 , G11C5/06 , G11C7/00 , G11C7/18 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/413 , G11C16/06 , H01L21/8239 , H01L27/105 , H03K19/177
CPC分类号： G11C7/18 , G11C5/025 , G11C8/12
摘要： An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
摘要翻译：阵列块具有至少两个子阵列块和第一互连路由信道，第一组局部互连线延伸穿过该第一互连路由信道。两个子阵列块中的每一个包括至少两个下级子阵列块和第二互连线路通道，第二组本地互连线延伸通过该第二互连线路通道。第一组本地互连线被配置为携带用于访问存储数据的存储位置或从哪个检索数据的输入信息，并且第二组局部互连线被配置为携带输入信息的子集。

68. 发明申请

WO99030240A1 MEMORY SYSTEM INCLUDING A MEMORY MODULE HAVING A MEMORY MODULE CONTROLLER 审中-公开
标题翻译：包含存储器模块控制器的存储器模块的存储器系统
公开(公告)号：WO99030240A1
公开(公告)日：1999-06-17
申请号：PCT/US1998/025181
申请日：1998-11-23
IPC分类号： G06F13/16 , G11C5/00 , G11C5/02 , G06F12/06
CPC分类号： G11C5/04 , G06F13/1689 , G06F13/1694 , G11C5/00 , G11C5/025
摘要： A system (300) that has a system memory controller (304) and memory module (306, 308). The memory modules (306, 308) include memory module controller (310, 316) coupled to the system memory controller (304) and a plurality of memory devices (312-315, 317-320) coupled to the memory module controllers (310, 316).
摘要翻译：一种具有系统存储器控制器（304）和存储器模块（306,308）的系统（300）。存储器模块（306,308）包括耦合到系统存储器控制器（304）的存储器模块控制器（310,316）和耦合到存储器模块控制器（310,316）的多个存储器设备（312-315,317-320） 316）。

69. 发明申请

WO99000752A1 METHOD AND APPARATUS FOR INCORPORATING DYNAMIC RANDOM ACCESS MEMORY DESIGN MODULES INTO AN INTEGRATED CIRCUIT CHIP DESIGN 审中-公开
标题翻译：将动态随机存取存储器设计模块并入集成电路芯片设计的方法和装置
公开(公告)号：WO99000752A1
公开(公告)日：1999-01-07
申请号：PCT/US1998/013340
申请日：1998-06-25
IPC分类号： G06F17/50 , G11C5/02 , G11C11/4097
CPC分类号： G06F17/5045 , G11C5/025 , G11C11/4097
摘要： An Electronic Design Automation (EDA) system (200) includes a plurality of pre-defined modules (212) to facilitate design of an Integrated Circuit (IC) which includes Dynamic Random Access Memory (DRAM). The pre-defined modules (212) include a plurality of modules which may be selected by an IC designer to include a DRAM of a specified organization and size in the IC. The pre-defined modules (212) include a plurality of core cell modules (216), each of the core cell modules (216) having a capacity, an organization and functional characteristics to allow use of a plurality of predefined combination of the core cells. The modules (212) also include a plurality of additional modules such as row decoders (226), column decoders (224), Bit-Line Sense Amplifiers (228), Bit-Line Sense Amplifier Drivers (218), Input/Output (I/O) buffers (220), and certain other miscellaneous support logic (215).
摘要翻译：电子设计自动化（EDA）系统（200）包括多个预定义模块（212），以便于包括动态随机存取存储器（DRAM）的集成电路（IC）的设计。预定义模块（212）包括可由IC设计者选择的多个模块，以在IC中包括指定组织和尺寸的DRAM。预定义模块（212）包括多个核心小区模块（216），每个核心小区模块（216）具有容量，组织和功能特征，以允许使用核心小区的多个预定组合。模块（212）还包括多个附加模块，例如行解码器（226），列解码器（224），位线检测放大器（228），位线检测放大器驱动器（218），输入/输出 / O）缓冲器（220）和某些其他辅助支持逻辑（215）。

70. 发明申请

WO1997027592A1 INTERDIGITATED MEMORY ARRAY 审中-公开
公开(公告)号：WO1997027592A1
公开(公告)日：1997-07-31
申请号：PCT/US1997000975
申请日：1997-01-17
申请人： CYPRESS SEMICONDUCTOR CORPORATION , REES, David, B.
发明人： CYPRESS SEMICONDUCTOR CORPORATION
IPC分类号： G11C05/06
CPC分类号： G11C5/025 , G11C5/063 , G11C8/10
摘要： A method and apparatus to eliminate the problem of requiring sizing of the row and column decoders according to the pitch of the cells in the memory array is to decouple the decoder cell pitch from the memory cell pitch without causing the chip area to increase dramatically. Decoupling is accomplished by driving the array from both sides for row drivers (42, 44) and by driving the array from both the top and bottom for column drivers (46, 48). Even numbered rows are driven from one side and odd numbered rows are driven from the other side. Alternating columns are driven from both the top and the bottom. For example, odd numbered columns are driven from the top while even numbered columns are driven from the bottom. In a second embodiment, predetermined rows are driven from one side while the other are driven from the other side. Similarly, predetermined columns may be driven from the top while the other are driven from the bottom. Rows (1 and 2) are driven from one side, rows (3 and 4) from the other, etc. Also, rows (1-3) may be driven from one side and rows (4-6) from the other, etc. Columns (1-2) may be driven from the top, (3-4) from the bottom, (5-6) from the top, etc. Again, columns (1-3) may be driven from the top and columns (4-6) driven from the bottom.
摘要翻译：消除根据存储器阵列中的单元的间距要求对行和列解码器进行尺寸调整的问题的方法和装置是将解码器单元间距与存储单元间距分离，而不会使芯片面积急剧增加。通过从两侧驱动阵列用于行驱动器（42,44）并且通过从列顶驱动器（46,48）的顶部和底部驱动阵列来实现去耦合。偶数行从一侧驱动，奇数行从另一侧驱动。交替的列从顶部和底部驱动。例如，从顶部驱动奇数列，而从底部驱动偶数列。在第二实施例中，从一侧驱动预定行，而从另一侧驱动另一行。类似地，可以从顶部驱动预定的列，而从底部驱动另一列。行（1和2）从一侧驱动，行（3和4）从另一侧驱动，等等。另外，行（1-3）可以从一侧驱动，并且行（4-6）从另一侧驱动，等柱（1-2）可以从顶部（3-4）从顶部驱动（3-4），从顶部驱动（5-6）等。同样，列（1-3）可以从顶部和列（4-6）从底部驱动。

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