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61. 发明申请

WO2007005218A1 APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：用于修复半导体存储器的装置和方法
公开(公告)号：WO2007005218A1
公开(公告)日：2007-01-11
申请号：PCT/US2006/023219
申请日：2006-06-14
申请人： MICRON TECHNOLOGY, INC. , MARTIN, Chris, G. , MANNING, Troy, A. , KEETH, Brent
发明人： MARTIN, Chris, G. , MANNING, Troy, A. , KEETH, Brent
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译：用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。当第一存储器访问对应于第一高速缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

62. 发明申请

WO2006105453A2 INTEGRATED CIRCUIT MEMORY ARRAY CONFIGURATION INCLUDING DECODING COMPATIBILITY WITH PARTIAL IMPLEMENTATION OF MULTIPLE MEMORY LAYERS 审中-公开
标题翻译：集成电路存储器阵列配置，包括解码兼容性，实现多个存储层的部分实现
公开(公告)号：WO2006105453A2
公开(公告)日：2006-10-05
申请号：PCT/US2006012106
申请日：2006-03-31
申请人： SANDISK 3D LLC , FASOLI LUCA G , SCHEUERLEIN ROY E
发明人： FASOLI LUCA G , SCHEUERLEIN ROY E
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C7/18 , G11C29/808 , H01L27/101 , H01L27/105 , Y10T29/49002
摘要： An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.
摘要翻译：具有三维存储器阵列的集成电路提供给定数量的存储器平面，但是可以通过省略与省略的存储器平面相关联的掩模和处理步骤来代替地包括较少数量的存储器层，而不改变任何用于其他存储器平面或其余设备的其他制造掩模，并且不需要对阵列的读取或读取/写入路径进行路由或其他配置更改。用于选择性地启用某些层选择器电路的控制电路是可配置的，并且层选择器电路被适当地布置，以将实现的存储器层上的相应阵列线耦合到每个相应的I / O总线，而与所实现的存储器平面的数量无关。

63. 发明申请

WO2005078736A1 半導体デバイス試験装置及び試験方法审中-公开
标题翻译：半导体器件测试装置和测试方法
公开(公告)号：WO2005078736A1
公开(公告)日：2005-08-25
申请号：PCT/JP2004/001805
申请日：2004-02-18
申请人：株式会社アドバンテスト , 大川和祥 , 荻野純子 , 吉永真之 , 本多元
发明人：大川和祥 , 荻野純子 , 吉永真之 , 本多元
IPC分类号： G11C29/00
CPC分类号： G11C29/56008 , G11C29/56 , G11C29/72 , G11C29/808 , G11C2029/5606
摘要：テストプロセサ（２０）により半導体メモリを内蔵するＤＵＴに試験信号を印加し、その応答信号に基いてメモリの良否を判定し、救済解析専用計算ユニット（３０）によりその試験結果を解析してメモリの欠陥セルをどのようにスペアラインで置き換えるかを決める半導体デバイス試験装置であって、救済解析専用計算ユニット（３０）は試験結果を記憶するフェイルメモリ部（３１）と、その試験結果をＭＲＡプログラムに従って解析すると共に、その解析処理単位間にユーザ解析プログラムのユーザ関数を挿入実行する汎用救済解析部（３２）とを有している。
摘要翻译：一种半导体器件测试装置，其中使用测试处理器（20）将测试信号施加到包括半导体存储器的DUT，基于响应信号执行存储器的故障/无故障测试，并且其中专用的补救分析计算单元（30）用于分析测试结果以决定如何在备用线路上更换存储器的有缺陷的单元。补救分析专用计算单元（30）具有用于存储测试结果的故障存储器部分（31）和用于根据MRA程序分析测试结果的通用补救分析部件（32），并且用于在分析处理单元，以及执行用户分析程序的用户功能。

64. 发明申请

WO2004053888A3 ZONE BOUNDARY ADJUSTMENT FOR DEFECTS IN NON-VOLATILE MEMORIES 审中-公开
标题翻译：非易失性存储器中的缺陷区域边界调整
公开(公告)号：WO2004053888A3
公开(公告)日：2004-09-30
申请号：PCT/US0338392
申请日：2003-12-02
申请人： SANDISK CORP
发明人： CONLEY KEVIN M
IPC分类号： G11C29/00 , G11C8/12 , G11C16/28
CPC分类号： G06F12/0246 , G11C16/04 , G11C29/4401 , G11C29/76 , G11C29/808
摘要： A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone boundaries are adjusted to accommodate defects allowed by memory test to improve card yields and to adjust boundaries in the field to extend the usable lifetime of the card. Firmware scans for the presence of defective blocks on the card. Once the locations of these blocks are known, the firmware calculates the zone boundaries in such a way that good blocks are equally distributed among the zones. Since the number of good blocks meets the card test criteria by the memory test criteria, defects will reduce card yield fallout. The controller can perform dynamic boundary adjustments. When defects occur, the controller can perform the analysis again and, if needed, redistributes the zone boundaries, moving any user data.
摘要翻译：非易失性存储器由卡控制器分为逻辑区，以减小其用于地址转换的数据结构的大小。调整区域边界以适应内存测试允许的缺陷，以提高卡片产量并调整现场边界以延长卡片的使用寿命。固件扫描卡上有缺陷块的存在。一旦这些块的位置被知道，固件就以这样的方式计算区域边界，使得好的块在这些区域之间是均匀分布的。由于良好块的数量符合内存测试标准的卡片测试标准，因此缺陷会降低卡片的成品率。控制器可以进行动态边界调整。当出现缺陷时，控制器可以再次执行分析，如果需要，可重新分配区域边界，移动任何用户数据。

65. 发明申请

WO02101749A9 METHODS AND APPARATUS FOR ANALYZING AND REPAIRING MEMORY 审中-公开
标题翻译：分析和修复记忆的方法和装置
公开(公告)号：WO02101749A9
公开(公告)日：2003-09-04
申请号：PCT/US0217744
申请日：2002-06-07
申请人： MITSUBISHI ELECTRIC CORP , SAUVAGEAU ANTHONY J , MULLINS MICHAEL A
发明人： SAUVAGEAU ANTHONY J , MULLINS MICHAEL A
IPC分类号： G11C29/44 , G11C29/00 , G11C29/04 , G11C7/00 , G11C8/00
CPC分类号： G11C29/72 , G11C29/808
摘要： Methods and apparatus for analyzing and repairing memory are presented. The method includes the step (302,304,306) of determining if failed memory cells detected in at least a portion of memory must be repaired using only one of a number of types of memory spares or may be repaired using any of the types of memory spares. Failed memory cells that must be repaired using only one of the number of types of memory spares are repeatedly repaired (308) skipping any failed memory cells that may be repaired using any of the number of types of memory spares, until either no new errors that must be repaired are repaired and no failed memory cells are skipped or memory is determined to not be repairable.
摘要翻译：介绍了分析和修复记忆体的方法和装置。该方法包括确定在至少一部分存储器中检测到的故障存储器单元是否必须仅使用多种类型的存储器备件中的一种来修复的步骤（302,304,306），或者可以使用任何类型的存储器备件进行修复。必须使用只有一种类型的内存备件修复的故障内存单元被重复修复（308）跳过任何可能使用任何数量类型的内存备件修复的故障内存单元，直到没有新的错误必须进行维修修理，并且不会跳过失败的内存单元，或将内存确定为不可修复。

66. 发明申请

WO2003012796A2 METHOD FOR SHARING REDUNDANT ROWS BETWEEN BANKS FOR IMPROVED REPARI EFFICIENCY 审中-公开
标题翻译：在改善偿付效率之间共享银行之间的冗余行的方法
公开(公告)号：WO2003012796A2
公开(公告)日：2003-02-13
申请号：PCT/US2002/023988
申请日：2002-07-29
申请人： MICRON TECHNOLOGY, INC.
发明人： BROWN, David, R. , DAUENBAUGH, Todd, A. , GAJAPATHY, Partha
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A method and corresponding architectures are disclosed for sharing redundant rows between banks of a memory array. The architecture is such that sub-arrays associated with different banks are alternated and coupled via a sense amp. In addition, sub-arrays belonging to the same bank are coupled via a single row decoder. This architecture allows for adjacent sub-arrays belonging to different banks to share redundant rows, thereby effectively doubling the number of redundant rows available for use in a given bank.
摘要翻译：公开了用于在存储器阵列的组之间共享冗余行的方法和相应的体系结构。该架构使得与不同存储体相关联的子阵列被交替并通过感测放大器耦合。此外，属于同一组的子阵列经由单行解码器耦合。该架构允许属于不同存储体的相邻子阵列共享冗余行，从而有效地将可用于给定存储体的冗余行的数量加倍。

67. 发明申请

WO1994003901A1 FAULT-TOLERANT, HIGH-SPEED BUS SYSTEM AND BUS INTERFACE FOR WAFER-SCALE INTEGRATION 审中-公开
标题翻译：容错集成的高速公交系统和总线接口
公开(公告)号：WO1994003901A1
公开(公告)日：1994-02-17
申请号：PCT/US1993007262
申请日：1993-08-05
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , LEUNG, Wing, Y. , HSU, Fu-Chieh
IPC分类号： G11C29/00
CPC分类号： H04L25/0272 , G06F11/006 , G06F11/10 , G06F11/1032 , G06F11/2007 , G06F12/0661 , G06F13/4077 , G11C5/04 , G11C29/006 , G11C29/08 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/81 , G11C29/832 , G11C29/88 , G11C2029/0401 , G11C2029/0411 , G11C2029/4402 , H01L22/22 , H01L27/0203 , H04L5/1461 , H04L25/026 , H04L25/028 , H04L25/029 , H04L25/0292 , Y10S257/907
摘要： A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the small bus; 5) use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) use of spare bus lines to provide local redundancy for the bus; and 9) use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.
摘要翻译：容错的高速晶片秤系统包括多个功能模块，对互连网络中的缺陷容错的并行分层总线以及一个或多个总线主机。该总线包括分段成多个总线线路，并通过互连网络中的可编程总线开关和总线收发器或中继器连接在一起。通过：1）使用小块大小（512K位）作为内存模块; 2）使用可编程标识寄存器来促进动态地址映射并相对容易地整合全局冗余; 3）使用总线的网格结构为互连网络提供全局冗余; 4）使用由13条信号线组成的较窄的总线，以保持小型公共汽车的总面积; 5）使用由可编程开关和可编程总线收发器连接的分段总线，以便于轻松隔离总线缺陷; 6）使用专用电路进行总线收发器和异步握手，方便动态总线配置; 7）使用可编程控制寄存器，方便运行时总线重新配置; 8）使用备用总线为总线提供局部冗余; 和9）在存储器模块中使用备用行和列提供局部冗余，获得分层总线中的高缺陷容限。

68. 发明申请

WO1993021578A1 INTEGRATED SEMICONDUCTOR MEMORY WITH REDUNDANCY ARRANGEMENT 审中-公开
标题翻译：冗余设备集成的半导体存储器
公开(公告)号：WO1993021578A1
公开(公告)日：1993-10-28
申请号：PCT/DE1992000316
申请日：1992-04-16
申请人： SIEMENS AKTIENGESELLSCHAFT , RIEGER, Johann , STECKER, Johann
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F11/16
CPC分类号： G11C29/781 , G11C29/806 , G11C29/808 , G11C29/846
摘要： An integrated semiconductor memory has a block decoder BKDEC with block selection signals BKS and several individually actuable memory field block units BK. The memory field block units BK have memory cells that can be driven by word and bit lines NWL, NBL, N &cir& NOt B &cir& NOt L &cir& NOt and redundant memory cells RMC that can be driven by redundant word lines RWL. The memory field block units BK have programmable redundant block decoders RBK that allow, together with redundant word line decoders RWDEC, redundant word lines RWL to be selected. When a redundant word line RWL is to be selected, only the memory field block unit BK in which the redundant word line RWL to be selected is contained is activated, thus suppressing the otherwise usual activation by means of a corresponding block selection signal BKS. The redundant word line RWL to be selected, together with its redundant memory cells RMC, needs therefore not be located in the same memory field block unit BK as the memory cells to be replaced, together with their normal word line NWL, but may also be located in (any) other memory field block unit BK. Integrated semiconductor memories may thus be produced with a higher yield.

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