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61. 发明申请

WO2006105039A3 MODEL CHECKING OF MULTI-THREADED SOFTWARE 审中-公开
标题翻译：多线程软件的型号检查
公开(公告)号：WO2006105039A3
公开(公告)日：2007-11-22
申请号：PCT/US2006011155
申请日：2006-03-27
申请人： NEC LAB AMERICA INC
发明人： KAHLON VINEET
IPC分类号： G06F9/44
CPC分类号： G06F11/3608
摘要： A technique for model checking of multi-threaded software is herein disclosed which advanta¬ geously can be used to verify correctness properties expressed using temporal logic, e.g., linear time temporal logic and branching time temporal logic. The model checking problem of a con¬ current system is decomposed into a plurality of model checking problems on individual threads of the multi-threaded software.
摘要翻译：本文公开了一种用于多线程软件的模型检查的技术，其有利地可用于验证使用时间逻辑（例如线性时间逻辑和分支时间时间逻辑）表达的正确性属性。该系统的模型检查问题被分解为多线程软件的各个线程上的多个模型检查问题。

62. 发明申请

WO2007041901A1 SYSTEM AND METHOD FOR FORMAL VERIFICATION OF STATECHARTS 审中-公开
标题翻译：系统和方法进行正式验证
公开(公告)号：WO2007041901A1
公开(公告)日：2007-04-19
申请号：PCT/CN2005/001690
申请日：2005-10-14
申请人： HONEYWELL INTERNATIONAL, INC. , ZHANG, Rui
发明人： ZHANG, Rui
IPC分类号： G06F11/28 , G06F9/45
CPC分类号： G06F11/28 , G06F11/3608
摘要： A system and method formally verifies a statechart. In an embodiment, an UML statechart is translated into an XML-based intermediate language. The XML intermediate language is then translated into a target format, and the target format is verified with a verification tool.
摘要翻译：系统和方法正式验证状态图。在一个实施例中，UML状态图被转换成基于XML的中间语言。然后将XML中间语言转换为目标格式，并使用验证工具验证目标格式。

63. 发明申请

WO2005072257A3 SYSTEM AND METHOD FOR MODELING, ABSTRACTION, AND ANALYSIS OF SOFTWARE 审中-公开
标题翻译：软件建模，抽取和分析的系统与方法
公开(公告)号：WO2005072257A3
公开(公告)日：2007-04-19
申请号：PCT/US2005001963
申请日：2005-01-21
申请人： NEC LAB AMERICA INC
发明人： IVANCIC FRANJO , ASHAR PRANAV N , GANAI MALAY K , GUPTA AARTI , YANG ZIJIANG
IPC分类号： G06F9/45 , G06F7/60 , G06F17/10 , G06F17/50
CPC分类号： G06F17/504 , G06F11/3608
摘要： A system and method is disclosed for formal verification of software that advantageously translates the software (101), which can have bounded recursion, into a Boolean representation (130) comprised of basic blocks and which applies SAT-based model checking (150) to the Boolean representation.
摘要翻译：公开了一种用于软件的形式验证的系统和方法，其有利地将可以具有有界递归的软件（101）转换成由基本块组成的布尔表示（130），并且将基于SAT的模型检查（150）应用于布尔表示法。

64. 发明申请

WO2004031946A1 XML INTERFACES IN UNIFIED RENDERING 审中-公开
标题翻译：统一渲染中的XML界面
公开(公告)号：WO2004031946A1
公开(公告)日：2004-04-15
申请号：PCT/EP2003/010442
申请日：2003-09-18
申请人： SAP AKTIENGESELLSCHAFT , DIETL, Josef , HAMMERICH, Reiner
发明人： DIETL, Josef , HAMMERICH, Reiner
IPC分类号： G06F9/44
CPC分类号： G06F11/3608 , G06F8/436 , G06F11/2294
摘要： Computer implemented method for validation of computer code, comprising providing a computer program by defining a set of definition instructions, a set of implementation instructions and a script code section, validating the defined sets using a validation tool, validating the script code section using the set of implementation instructions, wherein the definition instructions are classes and the implementation instructions are interfaces, wherein the definition instructions are converted into classes and the implementation instructions are converted into interfaces, wherein the definition instructions and said implementation instructions are described in XML.
摘要翻译：用于验证计算机代码的计算机实现方法，包括通过定义一组定义指令，一组实现指令和脚本代码部分来提供计算机程序，使用验证工具来验证所定义的集合，使用该集合来验证脚本代码部分的实现指令，其中定义指令是类，并且实现指令是接口，其中定义指令被转换成类，并且实现指令被转换为接口，其中定义指令和所述实现指令以XML描述。

65. 发明申请

WO02001362A2 DEBUGGING COORDINATION-CENTRIC SOFTWARE SYSTEMS BASED ON EXECUTIONS OF THE SOFTWARE SYSTEMS 审中-公开
标题翻译：根据软件系统执行情况调试协调中心软件系统
公开(公告)号：WO02001362A2
公开(公告)日：2002-01-03
申请号：PCT/US2001/019972
申请日：2001-06-22
IPC分类号： G06F9/44 , G06F9/46 , G06F11/36
CPC分类号： G06F8/36 , G06F9/4488 , G06F9/465 , G06F9/54 , G06F9/547 , G06F11/3608 , G06F11/3612 , G06F11/3632 , G06F11/3636 , G06F11/3664
摘要： Evolution diagrams can be used to graphically display operation of a distributed or concurrent software system to a programmer to aid in debugging. A preferred diagram explicitly shows selected events, message traffic between software components, changes in component behavior, and correlations between local behavior changes. Behavioral abstractions are typically a generalization of an event cluster. Behavioral abstraction is a technique where a predetermined behavioral sequence is automatically recognized by the simulator in a concurrent stream of system events. Behavioral abstraction allows a designer to create a model for a particular behavior and then set up a tool to find instances of the particular behavior in an execution trace. Cooperative execution is used to facilitate debugging distributed or concurrent software systems. Cooperative execution allows the software system to generate event records corresponding to system event. These event records can then be transferred to a debugging tool.
摘要翻译：演进图可用于将分布式或并发软件系统的操作图形显示给程序员，以帮助调试。优选图显式显示所选事件，软件组件之间的消息流量，组件行为的更改以及本地行为更改之间的相关性。行为抽象通常是事件集群的泛化。行为抽象是一种技术，其中预定的行为序列由并发的系统事件流由模拟器自动识别。行为抽象允许设计者为特定行为创建一个模型，然后设置一个工具来查找执行跟踪中特定行为的实例。合作执行用于方便调试分布式或并发软件系统。合作执行允许软件系统生成与系统事件相对应的事件记录。然后可以将这些事件记录传送到调试工具。

66. 发明申请

WO02001359A2 STATIC DEBUGGING TECHNIQUES FOR COORDINATION-CENTRIC SOFTWARE SYSTEMS 审中-公开
标题翻译：协调中心软件系统的静态调试技术
公开(公告)号：WO02001359A2
公开(公告)日：2002-01-03
申请号：PCT/US2001/020031
申请日：2001-06-22
IPC分类号： G06F9/44 , G06F9/46 , G06F11/36 , G06F11/00
CPC分类号： G06F8/36 , G06F9/4488 , G06F9/465 , G06F9/54 , G06F9/547 , G06F11/3608 , G06F11/3612 , G06F11/3632 , G06F11/3636 , G06F11/3664
摘要： Systemwide control aspects of a software system can be graphically-represented by a static control graph (SCG). A simple SCG typically has, the following: conjunctive nodes, each representing a control constraint; disjunctive nodes, each representing a mode within a component; and directed edges, each representing implication between a pair of nodes. Dynamic control graphs (DCGs) further have actions nodes, each representing an action that only responds to and generates control events, and lend themselves to a wider variety of dynamic checks and to model checking through conversion to Binary Decision Diagrams (BDDs) as well. Control dataflow graphs (CDGs) further have dataflow nodes, each representing a dataflow interaction of the software system and can be used to schedule components within the software system.
摘要翻译：软件系统的全系统控制方面可以由静态控制图（SCG）图形化表示。简单的SCG通常具有以下：连接节点，每个表示控制约束; 分离节点，每个节点代表组件内的模式; 和定向边缘，每个表示一对节点之间的含义。动态控制图（DCG）还具有动作节点，每个动作节点表示只响应并产生控制事件的动作，并且借助于更多种类的动态检查以及通过转换为二进制决策图（BDD）来建模检查。控制数据流图（CDG）还具有数据流节点，每个节点表示软件系统的数据流交互，可用于调度软件系统内的组件。

67. 发明申请

WO01082146A1 PROCEDURE FOR WORST-CASE ANALYSIS OF DISCRETE SYSTEMS 审中-公开
标题翻译：离散系统的分析案例分析程序
公开(公告)号：WO01082146A1
公开(公告)日：2001-11-01
申请号：PCT/US2001/040543
申请日：2001-04-18
IPC分类号： G06F17/50 , G06F11/36
CPC分类号： G06F11/3608
摘要： A general methodology for worst-case analysis of systems with discrete observable signals is disclosed. According to one embodiment, a signature (50) is chosen and a sigma -abstraction F (52) is created, based on the system and the particular property to be analyzed. This procedure requires a user to facilitate the creation of an appropriate signature and sigma -abstraction (53, 54). Next, for a given length of time T (58), a signature s is determined (58). From the signature s the worst-case boundary conditions are determined (60). The methodology may also be applied to timing analysis of embedded systems implemented on a single processor. The procedure calculates a time T which is an upper bound (60) on the time a processor can be busy (i.e. busy period). Thus, for the busy-period analysis, the time T is no longer fixed. As in the first embodiment, a signature sigma is selected and a sigma -abstraction F is created. A workload function R is chosen, and a signature s and time T are calculated. The calculated time T is an upper bound on the length of a busy period for the given system.
摘要翻译：公开了一种用于具有离散可观测信号的系统的最坏情况分析的一般方法。根据一个实施例，基于系统和要分析的特定属性，选择签名（50）并创建σ抽象F（52）。此过程要求用户方便创建适当的签名和sigma抽象（53,54）。接下来，对于给定的时间长度T（58），确定签名s（58）。从签名中确定最坏情况的边界条件（60）。该方法还可以应用于在单个处理器上实现的嵌入式系统的时序分析。该过程在处理器可以占线（即忙时间）时计算作为上限（60）的时间T。因此，对于繁忙期分析，时间T不再固定。与第一实施例一样，选择签名σ并创建sigma抽象F。选择工作负载函数R，并且计算签名s和时间T. 计算时间T是给定系统的忙时间长度的上限。

68. 发明申请

WO01001256A1 METHOD AND APPARATUS FOR STATIC ANALYSIS OF SOFTWARE CODE 审中-公开
标题翻译：软件代码静态分析的方法与装置
公开(公告)号：WO01001256A1
公开(公告)日：2001-01-04
申请号：PCT/US2000/018213
申请日：2000-06-29
IPC分类号： G06F9/45 , G06F11/36 , G06F9/44
CPC分类号： G06F11/3608 , G06F8/433
摘要： A method and apparatus for static analysis of program code. Embodiments of the invention allow for detection of run time bugs that may arise during the execution of a software application by implementing data structures that represent an image of the program and its variables in various execution instances. The invention is comprised of a context graph that represents various execution paths that are constructed from a series of related contexts. A context is a node in the context graph that represents the value of variables, state of methods, and the relationship between those variables and methods at an execution instance. The edges connecting the nodes represent one method calling the other, establishing a path of execution. Embodiments of the invention simplify the execution paths of large and complex programs into a context graph, using certain approximation and generalizations in analyzing the class files of a program. A context graph once developed can be queried for the status of different nodes and the relationship of those nodes at a certain instance of execution. Embodiments of the invention scale well to larger program codes, as they statistically represent information regarding various execution possibilities that are critical for analyzing the program, excluding any unnecessary details.
摘要翻译：一种用于程序代码静态分析的方法和装置。本发明的实施例允许通过在各种执行实例中实现表示程序的图像及其变量的数据结构来检测在执行软件应用期间可能出现的运行时间错误。本发明包括表示由一系列相关上下文构建的各种执行路径的上下文图。上下文是上下文图中的节点，它表示变量的值，方法的状态，以及执行实例的这些变量和方法之间的关系。连接节点的边缘表示一种调用另一种方法，建立执行路径。本发明的实施例使用某些近似和泛化来分析程序的类文件，将大型和复杂程序的执行路径简化为上下文图。一旦开发出的上下文图可以查询不同节点的状态，以及某些执行实例的那些节点的关系。本发明的实施例对较大的程序代码进行了扩展，因为它们统计地表示关于分析程序至关重要的各种执行可能性的信息，排除了任何不必要的细节。

69. 发明申请

WO9934302A8 AUTOMATIC GENERATION OF EVALUATION ORDER FOR A FUNCTION BLOCK DIAGRAM AND DETECTION OF ANY ASSOCIATED ERRORS 审中-公开
标题翻译：自动生成功能框图的评估订单和检测任何相关错误
公开(公告)号：WO9934302A8
公开(公告)日：1999-10-28
申请号：PCT/US9827702
申请日：1998-12-29
申请人： TRICONEX CORP
发明人： POWERS LESLIE V
IPC分类号： G05B19/05 , G06F11/36 , G06F15/46
CPC分类号： G06F11/3664 , G05B2219/23231 , G06F11/3608
摘要： The programming of programmable controllers and other sequential computing devices is facilitated by automatically generating an order for evaluating function blocks in a function diagram and by automatically detecting any errors in a function block diagram which would adversely affect the generation of a unique evaluation order, such as illegal cycles, disconnected subnetworks, and/or wired-OR connections. The nodes affected by the noted errors are graphically displayed to the user, who then may use a graphical interface to edit the network until all the noted errors have been corrected. A recursive procedure analogous to a topological sort may be used to automatically generate a unique evaluation order (11A, 11B, 17, 24, 12). The blocks upstream from each "maximal" output (15) are visited recursively from the input of one block (24, 13) to the output of a preceding block (17, 11A) until a "minimal" node (3) is reached.
摘要翻译：可编程控制器和其他顺序计算设备的编程通过自动生成用于评估功能图中的功能块的顺序以及通过自动检测功能框图中的任何错误，这将有助于产生独特的评估顺序（例如非法循环，断开的子网络和/或有线OR连接。受所述错误影响的节点图形显示给用户，然后用户可以使用图形界面来编辑网络，直到所有错误都被更正。可以使用类似于拓扑排序的递归过程来自动生成唯一的评估顺序（11A，11B，17,24，12）。从每个“最大”输出（15）上游的块被递归地从一个块（24,13）的输入访问到前一块（17,11A）的输出，直到达到“最小”节点（3）。

70. 发明申请

WO2016078716A1 METHOD AND DEVICE FOR AUTOMATICALLY VERIFYING A DESIGN OF A TECHNICAL SYSTEM 审中-公开
标题翻译：用于自动验证技术系统设计的方法和装置
公开(公告)号：WO2016078716A1
公开(公告)日：2016-05-26
申请号：PCT/EP2014/075153
申请日：2014-11-20
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： RICHTER, Jan
IPC分类号： G06F9/44
CPC分类号： G06F8/20 , G06F11/3608
摘要： The engineering and verifying process for a design of a technical system shall be improved. Therefore, there is provided a method for automatically bottom-up engineering and verifying including the steps of providing a specific first contract (C1) for a first component ( C 1 ) of the design and a specific second contract (C2) for a second component ( C 2 ) of the design, each specific contract characterizing all possible input and output values of the corresponding component, verifying the first contract (C1) and the second contract (C2), combining the first contract (C1) and the second contract (C2) to a common contract (C12) and verifying that the common contract (C12) is satisifable by a combination of the first contract (C1) and the second contract (C2), wherein verifying is performed by solving a mixed integer optimization problem. A similar method for automatically top-down engineering and verifying is also provided.
摘要翻译：改进技术体系设计的工程验证流程。因此，提供了一种用于自动自下而上的工程和验证的方法，包括为设计的第一组件（C1）提供特定的第一合同（C1）和用于第二组件的特定的第二合同（C2）的步骤（C1）和第二合同（C1）和第二合同（C2）的组合，确定相应组件的所有可能的输入和输出值， C2）到共同合同（C12），并通过第一合同（C1）和第二合同（C2）的组合来验证共同合同（C12）是否可以满足，其中通过求解混合整数优化问题来执行验证。还提供了类似的自动自顶向下工程和验证方法。

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