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51. 发明申请

WO2004017209A3 OPTIMIZED WRITE BACK FOR CONTEXT SWITCHING 审中-公开
标题翻译：用于上下文切换的优化写回
公开(公告)号：WO2004017209A3
公开(公告)日：2004-08-05
申请号：PCT/IB0303262
申请日：2003-07-17
申请人： KONINKL PHILIPS ELECTRONICS NV , KOSTELIJK ANTON P
发明人： KOSTELIJK ANTON P
IPC分类号： G06F9/30 , G06F12/08 , G06F12/12
CPC分类号： G06F9/30021 , G06F12/0804 , G06F12/0875
摘要： An electronic device (200) has a data processing unit (220) with access to a memory architecture including a main memory (240) and a cache (260) under control of data management circuitry (280). The cache lines (264) of cache (260) are extended with a field (262) for storing a data difference bit pattern indicating a difference between the data element in the cache line (264) and the corresponding data element in the main memory (240). Data management circuitry (280) incorporates a first data storage element (282) and a second data storage element (284) for storing references to the boundaries of a contiguous stack or frame of data elements in main memory (240). When the data elements in the data frame have become irrelevant, control circuitry (286) generates relevant references to the data elements in the frame and further control circuitry (288) compares those references with the references stored in the cache lines (264). If a match is found, the corresponding data difference bit pattern is set to a value indicating the absence of a difference between the data element in the cache line (264) and the corresponding data element in the main memory (240) without writing back the data element from the cache (260) to main memory (240).
摘要翻译：电子设备（200）具有在数据管理电路（280）的控制下访问包括主存储器（240）和高速缓存（260）的存储器架构的数据处理单元（220）。高速缓存（260）的高速缓存行（264）用用于存储指示高速缓存行（264）中的数据元素与主存储器中的相应数据元素之间的差的数据差异位模式的字段（262）进行扩展 240）。数据管理电路（280）包括第一数据存储元件（282）和第二数据存储元件（284），用于存储对主存储器（240）中的连续堆栈或数据元素的边界的引用。当数据帧中的数据元素变得不相关时，控制电路（286）产生对帧中的数据元素的相关引用，并且另外的控制电路（288）将这些引用与存储在高速缓存行（264）中的引用进行比较。如果找到匹配，则相应的数据差异位模式被设置为指示高速缓存行（264）中的数据元素与主存储器（240）中的相应数据元素之间不存在差异的值，而不写回数据元素从高速缓存（260）到主存储器（240）。

52. 发明申请

WO2004046933A1 メモリ制御装置およびキャッシュリプレース制御方法审中-公开
标题翻译：内存控制器和缓存更换控制方法
公开(公告)号：WO2004046933A1
公开(公告)日：2004-06-03
申请号：PCT/JP2002/012137
申请日：2002-11-20
申请人：富士通株式会社 , 中尾学
发明人：中尾学
IPC分类号： G06F12/12
CPC分类号： G06F12/123
摘要： A memory controller comprising a single-port LRU RAM (26) holding replacement way information on replacement of a cache memory (a cache tag RAM (22) and a cache data RAM (23)), an LRU replacement way selecting section (27) for selecting a way to be replaced by an LRU algorithm depending on the replacement way information on the single-port LRU RAM (26), a random replacement way selecting section (105) for selecting a way to be replaced randomly without using the replacement way information, a hit decision section (102) for carrying out hit decision about first and second requests simultaneously made for an access to a cache memory by a CPU (10), and an arbiter section (104) for, if the hit decisions about the first and second requests are both cache misses, allowing the LRU replacement way selecting section (27) to select a way in response to the first request and allowing the random replacement way selecting section (105) to select a way in response to the second request.
摘要翻译：一种存储器控制器，包括保存有关高速缓存存储器（高速缓存标签RAM（22）和高速缓冲存储器数据RAM（23））的更换的替换路信息的单端口LRU RAM（26），LRU替换路径选择部分（27）用于根据单端口LRU RAM（26）上的替代方式信息来选择要由LRU算法代替的方式，随机替换方式选择部分（105），用于选择随机替换的方式，而不使用替换方式信息，用于执行关于由CPU（10）访问高速缓冲存储器而同时进行的第一和第二请求的命中决定的命中决定部分（102），以及仲裁器部分（104），如果关于第一和第二请求都是高速缓存未命中，允许LRU替换方式选择部分（27）响应于第一请求选择一种方式，并允许随机替换方式选择部分（105）响应于第二请求选择一种方式。

53. 发明申请

WO2004046920A2 PROCESSOR CACHE MEMORY AS RAM FOR EXECUTION OF BOOT CODE 审中-公开
标题翻译：处理器缓存内存作为执行引擎代码的RAM
公开(公告)号：WO2004046920A2
公开(公告)日：2004-06-03
申请号：PCT/US0334808
申请日：2003-10-30
申请人： INTEL CORP
发明人： DATTA SHAM , ZIMMER VINCENT , VAID KUSHAGRA , STEVENS WILLIAM , SANTONI AMY
IPC分类号： G06F9/445 , G06F12/08 , G06F12/12
CPC分类号： G06F12/126 , G06F9/4403 , G06F12/0862 , G06F2212/2515
摘要： In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.
摘要翻译：在一个实施例中，计算机引导方法允许为具有多个交叉处理器交互的高速缓存选择预定数据块对齐。作为RAM系统的缓存的高速缓存RAM列被加载有标签以防止意外的高速缓存行驱逐，并且执行引导代码，其中预先加载的高速缓存RAM作为存储器存储器显示在执行的引导代码流中。

54. 发明申请

WO0188720A3 SYSTEM AND METHOD FOR HIGH-SPEED SUBSTITUTE CACHE 审中-公开
标题翻译：高速替代缓存的系统和方法
公开(公告)号：WO0188720A3
公开(公告)日：2003-10-02
申请号：PCT/US0114088
申请日：2001-05-02
申请人： SUPERSPEED SOFTWARE INC
发明人： DEMPSEY MICHAEL , DICKMAN ERIC
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0866 , G06F12/0804 , G06F12/123 , G06F2212/311
摘要： Methods of caching data in a computer wherein a cache is given a number of caching parameters. In a method for caching data in a computer having an operating system with a file caching mechanism, the file caching mechanism is selectively disabled and a direct block cache is accessed to satisfy a request of the request stream. Cache memory can be expanded by allocating memory to a memory table created in a user mode portion of the computer and having a set of virtual memory addresses. Methods of caching data can include creating an associative map, and optimizing the order of writes to a disk with a lazy writer. Methods are further assisted by displaying cache performance criteria on a user interface and allowing user adjustment of caching parameters such as cache size, cache block size and lazy writer aggressiveness. A user may further be given the ability to enable or disable a cache for a given selected disk volume.
摘要翻译：在计算机中缓存数据的方法，其中缓存被给予多个缓存参数。在具有具有文件缓存机制的操作系统的计算机中缓存数据的方法中，选择性地禁用文件缓存机制，并且访问直接块高速缓存以满足请求流的请求。可以通过将内存分配给在计算机的用户模式部分中创建并具有一组虚拟存储器地址的存储器表来扩展缓存存储器。缓存数据的方法可以包括创建关联映射，并且利用懒惰的作者来优化写入磁盘的顺序。通过在用户界面上显示缓存性能标准并允许用户调整高速缓存参数（如高速缓存大小，缓存块大小和惰性写入器侵略性）来进一步协助方法。还可以向用户赋予为给定的所选磁盘卷启用或禁用高速缓存的能力。

55. 发明申请

WO2002093386A1 SECTORED LEAST-RECENTLY-USED CACHE REPLACEMENT 审中-公开
标题翻译：部署最少最近使用的高速缓存更换
公开(公告)号：WO2002093386A1
公开(公告)日：2002-11-21
申请号：PCT/US2002/008807
申请日：2002-03-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： SANDER, Benjamin, T. , TAN, Teik-Chung , DULEY, Adam
IPC分类号： G06F12/12
CPC分类号： G06F12/128 , G06F12/0864
摘要： Various methods and systems for implementing a sectored least recently used (LRU) cache replacement algorithm are disclosed. Each set in an N-way set-associative cache (100) is partitioned into several sectors that each include two or more of the N ways. Usage status indicators such as pointers (14) show the relative usage status of the sectors in an associated set. For example, an LRU pointer may point to the LRU sector, an MRU pointer may point to the MRU sector, and so on. When a replacement is performed, a way within the LRU sector identified by the LRU pointer is filled.
摘要翻译：公开了用于实现最近最少使用的（LRU）高速缓存替换算法的各种方法和系统。 N路组合关联高速缓存（100）中的每个集合被划分为几个扇区，每个扇区包括N个方式中的两个或更多个。使用状态指示符（如指针（14））显示相关组中扇区的相对使用状态。例如，LRU指针可以指向LRU扇区，MRU指针可以指向MRU扇区，依此类推。当执行替换时，由LRU指针识别的LRU扇区内的方式被填充。

56. 发明申请

WO02054256A2 METHOD AND APPARATUS FOR OPTIMIZING DATA STREAMING IN A COMPUTER SYSTEM UTILIZING RANDOM ACCESS MEMORY IN A SYSTEM LOGIC DEVICE 审中-公开
标题翻译：在系统逻辑设备中利用随机访问存储器的计算机系统中优化数据流的方法和装置
公开(公告)号：WO02054256A2
公开(公告)日：2002-07-11
申请号：PCT/US2001/050414
申请日：2001-12-20
IPC分类号： G06F12/12 , G06F13/00
CPC分类号： G06F12/126
摘要： One embodiment of an apparatus for optimizing data streaming in a computer system between a processor and a system component includes a cache in a system logic device that stores disposable information. The term "disposable information" is defined as information that is meant to be read by a system component only once. Once a particular cache entry containing disposable information is read by a system component, that cache entry may be overwritten. Because disposable information is meant to be read only once, there is no need for the cache to write the information to system memory before overwriting the cache entry.
摘要翻译：用于优化处理器和系统组件之间的计算机系统中的数据流的装置的一个实施例包括存储一次性信息的系统逻辑设备中的高速缓存。术语“一次性信息”被定义为仅由系统组件读取一次的信息。一旦包含一次性信息的特定高速缓存条目被系统组件读取，则该高速缓存条目可被覆盖。因为一次性信息意味着只读一次，所以在覆盖高速缓存条目之前不需要缓存将信息写入系统存储器。

57. 发明申请

WO0057276A9 METHOD AND APPARATUS FOR POINTER RELOCATION OPTIMIZATION FOR VIRTUAL MEMORY MAPPING AND TRANSACTION MANAGEMENT IN A DATABASE SYSTEM 审中-公开
标题翻译：数据库系统中虚拟内存映射和交易管理的指针定位优化方法与装置
公开(公告)号：WO0057276A9
公开(公告)日：2002-06-27
申请号：PCT/US0008085
申请日：2000-03-24
申请人： EXCELON CORP
发明人： LEIVENT JONATHAN I
IPC分类号： G06F12/00 , G06F12/08 , G06F12/10 , G06F12/12 , G06F17/30
CPC分类号： G06F17/30607 , G06F12/0866 , G06F12/1045 , G06F12/123
摘要： For an object-oriented database system, an apparatus for virtual memory mapping and transaction management comprises at least one permanent storage and at least one database, at least one cache, and a processing unit including means, utilizing virtual addresses, to access data in the cache, means for mapping virtual to physical addresses, and means for retaining the cached data after a transaction. Data retained across transations will often not need further translation, referred to as forward relocation. Making cached data usable across a sequence of transactions often without requiring further translation, while working size of this data may be larger than a client computer's address space, is referred to as relocation optimization. The method uses a queue containing entities ordered by recency of use, and recycles address space of least-recently used bindings to preserve the validity of bindings necessary for the proper function of the client application with minimal overhead.
摘要翻译：对于面向对象的数据库系统，用于虚拟存储器映射和事务处理的装置包括至少一个永久存储器和至少一个数据库，至少一个高速缓存和包括使用虚拟地址的装置来访问数据的装置缓存，用于映射虚拟到物理地址的手段，以及用于在事务之后保留高速缓存的数据的装置。通过跨过程保留的数据通常不需要进一步的翻译，称为向前迁移。使缓存的数据在一系列事务中可用，通常不需要进一步的翻译，而该数据的工作大小可能大于客户端计算机的地址空间，被称为重定位优化。该方法使用包含按照使用次序排序的实体的队列，并回收最近最少使用的绑定的地址空间，以最小的开销来保留客户端应用程序的正常功能所必需的绑定的有效性。

58. 发明申请

WO02039284A2 SYSTEMS AND METHODS FOR MANAGEMENT OF MEMORY 审中-公开
标题翻译：用于管理存储器的系统和方法
公开(公告)号：WO02039284A2
公开(公告)日：2002-05-16
申请号：PCT/US2001/045500
申请日：2001-11-02
IPC分类号： G06F12/12 , G06F12/00
CPC分类号： G06F12/122 , G06F12/123
摘要： Memory management systems and methods that may be employed, for example, to provide efficient management of memory for network systems. The disclosed systems and methods may utilize a multi-layer queue management structure to manage buffer/cache memory in an integrated fashion. The disclosed systems and methods may be implemented as part of an information management system, such as a network processing system that is operable to process information communicated via a network environment, and that may include a network processor operable to process network-communicated information and a memory management system operable to reference the information based upon a connection status associated with the content.
摘要翻译：可用于例如为网络系统提供对存储器的有效管理的内存管理系统和方法。所公开的系统和方法可以利用多层队列管理结构以集成的方式来管理缓冲器/高速缓冲存储器。所公开的系统和方法可以被实现为信息管理系统的一部分，诸如可操作以处理经由网络环境传送的信息的网络处理系统，并且可以包括可操作以处理网络传送的信息的网络处理器和存储器管理系统，其可操作以基于与所述内容相关联的连接状态来引用所述信息。

59. 发明申请

WO0152067A3 METHOD AND SYSTEM FOR IMPLEMENTING MEMORY EFFICIENT TRACK AGING 审中-公开
标题翻译：实现记忆效应跟踪老化的方法和系统
公开(公告)号：WO0152067A3
公开(公告)日：2002-03-07
申请号：PCT/US0100556
申请日：2001-01-04
申请人： STORAGE TECHNOLOGY CORP
发明人： VANDENBERGH HENK , MILILLO MICHAEL S , PETERSON GREGORY W
IPC分类号： G06F12/12
CPC分类号： G06F12/123
摘要： Each time a track is referenced, a value representing the last referenced age is entered for a track entry in a last referenced age table (LRAT). The last referenced age table is indexed by track. A second table, an age frequency table (AFT), counts all segments in use in each reference age. The AFT is indexed by the reference age of the tracks. When a track is referenced, the number of segments used for the track is added to a segment count associated with the last referenced age of the track. The segment count tallies the total number of segments in use for the reference age for all tracks referenced to that age. The number of segments used for the previous last referenced age of the track is subtracted from the segment count associated with the previous last referenced age in the AFT. When free space is needed, tracks are discarded from the LRAT by reference age, the oldest first. The range of ages to be discarded in the LRAT is calculated in the AFT by counting the total amount of segments used by each reference age until the total number of segments needed is realized. Counting is started at the AFT entry with the oldest reference age. The reference age of the last counted entry in the AFT is the discard age. The LRAT is scanned for reference ages between the old age and the discard age, and those reference ages are discarded.
摘要翻译：每次轨道被引用时，都会为最后一次参考的年龄表（LRAT）中的轨道条目输入代表最后参考年龄的值。最后参考的年龄表按轨道索引。第二个表格，年龄频率表（AFT）计算每个参考年龄使用的所有细分。 AFT由轨道的参考年龄索引。当轨道被引用时，用于轨道的段的数量被添加到与轨道的最后参考年龄相关联的段计数。段计数与参考该年龄的所有轨道的参考年龄的总共段数一致。用于前一次参考年龄的段的数量从与AFT中前一个参考年龄相关联的段计数中减去。当需要可用空间时，轨道将从LRAT中被丢弃，参考年龄是最早的。通过计算每个参考年龄段使用的段的总数，直到实现所需段的总数，在AFT中计算要在LRAT中舍弃的年龄范围。计数开始于具有最早参考年龄的AFT条目。 AFT最后一次入场的参考年龄是丢弃年龄。扫描LRAT在旧年龄和丢弃年龄之间参考年龄，并丢弃那些参考年龄。

60. 发明申请

WO0150269A3 A METHOD AND APPARATUS TO PERFORM A ROUND ROBIN AND LOCKING CACHE REPLACEMENT SCHEME 审中-公开
标题翻译：一种执行环形罗宾和锁定缓存更换方案的方法和装置
公开(公告)号：WO0150269A3
公开(公告)日：2001-12-13
申请号：PCT/US0042305
申请日：2000-11-27
申请人： INTEL CORP , CLARK LAWRENCE T , CLARK MATTHEW M
发明人： CLARK LAWRENCE T , CLARK MATTHEW M
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
CPC分类号： G06F12/126 , G06F12/1027
摘要： A first plurality of registers are daisy chained together with each register associated with a particular cache line. Similarly, a second plurality of registers are daisy chained together with each register associated with a cache line. The first daisy chain defines a fill order of cache lines and the second daisy chain defines a lock order for the cache lines.
摘要翻译：第一组多个寄存器与与特定高速缓存线相关联的每个寄存器串联在一起。类似地，第二多个寄存器与与高速缓存行相关联的每个寄存器串联在一起。第一个菊花链定义了缓存线的填充顺序，第二个菊花链定义了高速缓存行的锁定顺序。

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