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51. 发明申请

WO2017052631A1 PSTTM DEVICE WITH MULTI-LAYERED FILTER STACK 审中-公开
标题翻译：具有多层过滤器堆叠的PSTTM设备
公开(公告)号：WO2017052631A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052383
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： OGUZ, Kaan , O'BRIEN, Kevin P. , WIEGAND, Christopher J. , RAHMAN, MD Tofizur , DOYLE, Brian S. , DOCZY, Mark L. , GOLONZKA, Oleg , GHANI, Tahir , BROCKMAN, Justin S.
IPC分类号： H01L43/02 , H01L43/10 , H01L43/12
CPC分类号： H01L43/12 , H01F10/3272 , H01F10/3286 , H01F41/307 , H01L43/08 , H01L43/10
摘要： MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.
摘要翻译： MTJ材料堆栈，采用这种堆栈的pSTTM设备，以及采用这种pSTTM设备的计算平台。在一些实施例中，垂直MTJ材料堆叠包括设置在固定磁性层和反铁磁层或合成反铁磁（SAF）堆叠之间的多层过滤器堆叠。在一些实施例中，过滤器堆叠的非磁性层包括Ta，Mo，Nb，W或Hf中的至少一种。这些过渡金属可以是纯的形式或与其它成分合金化。

52. 发明申请

WO2017052611A1 NANOWIRE TRANSISTOR DEVICE ARCHITECTURES 审中-公开
标题翻译：纳米晶体管器件结构
公开(公告)号：WO2017052611A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052305
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： MEHANDRU, Rishabh , GHANI, Tahir , LIAO, Szuya S. , KIM, Seiyon
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42364 , H01L29/42392 , H01L29/775 , H01L2029/42388
摘要： Techniques are disclosed for forming nanowire transistor architectures in which the presence of gate material between neighboring nanowires is eliminated or otherwise reduced. In accordance with some embodiments, neighboring nanowires can be formed sufficiently proximate one another such that their respective gate dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous dielectric layer shared by the neighboring nanowires. In some cases, a given gate dielectric layer may be of a multi-layer configuration, having two or more constituent dielectric layers. Thus, in accordance with some embodiments, the gate dielectric layers of neighboring nanowires may be formed such that one or more constituent dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous constituent dielectric layer shared by the neighboring nanowires.
摘要翻译：公开了用于形成纳米线晶体管架构的技术，其中相邻纳米线之间的栅极材料的存在被消除或以其它方式减少。根据一些实施例，相邻的纳米线可以充分地彼此靠近地形成，使得它们各自的栅极电介质层是：（1）仅彼此接触（例如，是连续的）; 或（2）彼此合并以提供由相邻纳米线共享的单个连续的介电层。在一些情况下，给定的栅极介电层可以是具有两个或多个构成介电层的多层结构。因此，根据一些实施例，可以形成相邻纳米线的栅极电介质层，使得一个或多个构成电介质层是：（1）仅彼此接触（例如，是连续的）; 或（2）彼此合并以提供由相邻纳米线共享的单个连续的构成介电层。

53. 发明申请

WO2017052601A1 TECHNIQUES FOR CONTROLLING TRANSISTOR SUB-FIN LEAKAGE 审中-公开
标题翻译：用于控制晶体管子阱漏电的技术
公开(公告)号：WO2017052601A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052280
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , MAJHI, Prashant , MURTHY, Anand S. , GHANI, Tahir , AUBERTINE, Daniel B. , MEYER, Heidi M. , JAMBUNATHAN, Karthik , BHIMARASETTI, Gopinath
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1079 , B82Y10/00 , H01L29/0673 , H01L29/66439 , H01L29/66803 , H01L29/775 , H01L29/785
摘要： Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.
摘要翻译：公开了用于控制晶体管子鳍片泄漏的技术。这些技术可用于高度尺度的finFET以及其他非平面晶体管。在一些情况下，这些技术包括暴露形成在衬底上的翅片结构的中间部分，然后经由掺杂或氧化过程将暴露部分转化为电绝缘材料。例如，可以使用单层掺杂（MLD）工艺将掺杂剂以自饱和单层方案输送到散热片的暴露部分。在另一示例性情况下，可以使用热氧化来将暴露部分转换成绝缘体材料。在一些情况下，阻挡层（例如，包括碳掺杂）可以位于鳍的暴露部分上方，以帮助防止掺杂或氧化过程影响用于晶体管沟道的鳍的上部区域。

54. 发明申请

WO2017003414A1 LOW DAMAGE SELF-ALIGNED AMPHOTERIC FINFET TIP DOPING 审中-公开
标题翻译：低损耗自对准AMPHOTERIC FINFET TIP DOPING
公开(公告)号：WO2017003414A1
公开(公告)日：2017-01-05
申请号：PCT/US2015/038197
申请日：2015-06-27
申请人： INTEL CORPORATION
发明人： KAVALIEROS, Jack T. , MOHAPATRA, Chandra S. , MURTHY, Anand S. , RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , GHANI, Tahir , KENNEL, Harold W.
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/2258 , H01L21/8258 , H01L29/205 , H01L29/66522 , H01L29/66545 , H01L29/66803
摘要： Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.
摘要翻译：包括设置在第二III-V族化合物半导体上的第一III-V族化合物半导体材料中的多数载流子通道的单片finFET。虽然诸如牺牲栅极堆叠的掩模覆盖沟道区，但两性掺杂剂的源沉积在暴露的翅片侧壁上并扩散到第一III-V族化合物半导体材料中。两性掺杂剂优选地在第一III-V材料内作为供体激活，并且具有第二III-V材料的受体，从而在第一和第二III-V材料之间提供晶体管尖端掺杂p-n结。沉积横向间隔件以覆盖翅片的尖端部分。未被掩模或间隔物覆盖的鳍的区域中的源极/漏极区域通过尖端区域电耦合到沟道。通道掩码被门堆叠替换。

55. 发明申请

WO2017003411A1 MULTI-HEIGHT FINFET DEVICE BY SELECTIVE OXIDATION 审中-公开
标题翻译：通过选择性氧化的多高度FINFET器件
公开(公告)号：WO2017003411A1
公开(公告)日：2017-01-05
申请号：PCT/US2015/038194
申请日：2015-06-27
申请人： INTEL CORPORATION
发明人： KIM, Seiyon , BHIMARASETTI, Gopinath , RIOS, Rafael , KAVALIEROS, Jack T. , GHANI, Tahir , MURTHY, Anand S. , MEHANDRU, Rishabh
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/02233 , H01L21/02546 , H01L23/49827 , H01L23/49838 , H01L27/0886 , H01L27/1211 , H01L29/0847 , H01L29/1037 , H01L29/66545 , H01L29/78 , H01L29/785 , H01L29/7851
摘要： A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.
摘要翻译：一种方法，包括在衬底上形成多栅极器件的非平面导电沟道，所述沟道包括从所述衬底的表面处的基底限定的高度尺寸; 修改小于通道的整个部分; 以及在所述沟道上形成栅极堆叠，所述栅极堆叠包括电介质材料和栅电极。一种包括在基板上的非平面多栅极器件的装置，包括包括限定导电部分的高度尺寸的沟道和设置在沟道上的氧化部分和栅极堆叠，栅极堆叠包括电介质材料和栅电极。

56. 发明申请

WO2016209220A1 REPLACEMENT CHANNEL ETCH FOR HIGH QUALITY INTERFACE 审中-公开
标题翻译：更换高质量接口的通道
公开(公告)号：WO2016209220A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/037344
申请日：2015-06-24
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , PANG, Ying , MISTKAWI, Nabil G. , MURTHY, Anand S. , GHANI, Tahir , CHAO, Huang-Lin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/02532 , H01L21/02546 , H01L21/823481 , H01L21/823814 , H01L21/823821 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1054 , H01L29/161 , H01L29/20 , H01L29/6681
摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.
摘要翻译：公开了用于定制鳍式晶体管器件以提供不同范围的通道配置和/或材料系统以及在同一集成电路管芯内的技术。牺牲翅片通过湿和/或干蚀刻化学物质去除，其被配置为提供非面的沟槽底部，并且没有或以其它方式低离子损伤。然后用期望的半导体材料填充沟槽。具有低离子损伤和非刻面形态的沟槽底部促进了衬底和替换材料之间的无缺陷或低缺陷界面。在一个实施例中，第一组牺牲硅散热片中的每一个被凹入并用p型材料代替，并且第二组牺牲散热片中的每一个凹进并用n型材料代替。另一个实施例可以包括天然散热片（例如Si）和替代翅片（例如，SiGe）的组合。另一实施例可以包括全部相同配置的替换散热片。

57. 发明申请

WO2016209219A1 SUB-FIN SIDEWALL PASSIVATION IN REPLACEMENT CHANNEL FINFETS 审中-公开
标题翻译：更换通道熔体中的细小的边缘钝化
公开(公告)号：WO2016209219A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/037326
申请日：2015-06-24
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , PANG, Ying , MURTHY, Anand S. , GHANI, Tahir , JAMBUNATHAN, Karthik
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/408 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1054 , H01L29/16 , H01L29/20 , H01L29/42392 , H01L29/6681 , H01L29/775 , H01L29/7851 , H01L29/78696
摘要： Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.
摘要翻译：公开了通过使用亚翅片钝化层来减少鳍状晶体管的截止状态泄漏的技术。在一些情况下，这些技术包括在体硅衬底中形成牺牲翅片并沉积和平坦化浅沟槽隔离（STI）材料，用替换材料（例如SiGe或III-V材料）去除和替换牺牲硅散热片，去除 STI材料的至少一部分以暴露替代翅片的副鳍片区域，向暴露的子鳍片施加钝化层/处理剂/试剂，以及重新沉积和平坦化另外的STI材料。然后可以执行标准晶体管形成工艺以完成晶体管器件。这些技术通常提供为在基于STI的沟槽中生长的结构添加任意钝化层的能力。钝化层抑制子鳍源极到漏极（和漏极到源极）的电流泄漏。

58. 发明申请

WO2016105437A1 HIGH MOBILITY NANOWIRE FIN CHANNEL ON SILICON SUBSTRATE FORMED USING SACRIFICIAL SUB-FIN 审中-公开
标题翻译：使用SACRIFICIAL SUB-FIN形成的硅基板上的高移动性NANOWIRE FIN通道
公开(公告)号：WO2016105437A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072448
申请日：2014-12-26
申请人： INTEL CORPORATION , DEWEY, Gilbert , METZ, Matthew V. , KAVALIEROS, Jack T. , RACHMADY, Willy , GHANI, Tahir , MURTHY, Anand S. , MOHAPATRA, Chandra S. , GARDNER, Sanaz K. , RADOSAVLJEVIC, Marko , GLASS, Glenn A.
发明人： DEWEY, Gilbert , METZ, Matthew V. , KAVALIEROS, Jack T. , RACHMADY, Willy , GHANI, Tahir , MURTHY, Anand S. , MOHAPATRA, Chandra S. , GARDNER, Sanaz K. , RADOSAVLJEVIC, Marko , GLASS, Glenn A.
IPC分类号： H01L21/762 , H01L21/20 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02532 , H01L21/02546 , H01L21/02603 , H01L21/02639 , H01L21/30604 , H01L21/31111 , H01L21/7605 , H01L21/762 , H01L21/76224 , H01L29/045 , H01L29/0649 , H01L29/122 , H01L29/161 , H01L29/20 , H01L29/66469 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.
摘要翻译：集成电路管芯包括用于晶体管（例如，作为MOS器件的沟道的单个材料或堆叠）的沟道材料的四栅极器件纳米线，其通过从沟道材料的下方去除一部分子鳍材料而形成，其中亚翅片材料在长宽比捕集（ART）沟槽中生长。在某些情况下，在形成这样的纳米线时，可以去除通道下的有缺陷的翅片材料或区域。这种去除隔离了翅片通道，去除了翅片缺陷和泄漏路径，并且形成具有四个暴露表面的通道材料的纳米线，栅极材料可以形成在其上。

59. 发明申请

WO2016105426A1 INGAAS EPI STRUCTURE AND WET ETCH PROCESS FOR ENABLING III-V GAA IN ART TRENCH 审中-公开
标题翻译： INGAAS EPI结构和湿蚀刻工艺，用于在ART TRENCH中启用III-V GAA
公开(公告)号：WO2016105426A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072396
申请日：2014-12-24
申请人： INTEL CORPORATION
发明人： GARDNER, Sanaz K. , RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , KAVALIEROS, Jack T. , MOHAPATRA, Chandra S. , MURTHY, Anand S. , RAHHAL-ORABI, Nadia M. , ZELICK, Nancy M. , GHANI, Tahir
IPC分类号： H01L21/762 , H01L21/336 , H01L29/78
CPC分类号： H01L29/0673 , H01L21/76224 , H01L29/045 , H01L29/0649 , H01L29/205 , H01L29/267 , H01L29/66522 , H01L29/66545 , H01L29/785
摘要： Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.
摘要翻译：本发明的实施例包括纳米线和纳米棒状晶体管以及形成这种晶体管的方法。根据实施例，用于形成微电子器件的方法可以包括在形成于浅沟槽隔离（STI）层中的沟槽内形成多层堆叠。多层堆叠可以包括至少沟道层，形成在沟道层下面的释放层，以及形成在沟道层下面的缓冲层。 STI层可以凹入，使得STI层的顶表面在释放层的顶表面下方。通过相对于沟道层选择性地蚀刻剥离层，从沟道层下方暴露的剥离层。

60. 发明申请

WO2016105404A1 THIN CHANNEL REGION ON WIDE SUBFIN 审中-公开
标题翻译：窄沟槽区域
公开(公告)号：WO2016105404A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072276
申请日：2014-12-23
申请人： INTEL CORPORATION
发明人： GARDNER, Sanaz K. , RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , KAVALIEROS, Jack T. , MOHAPATRA, Chandra S. , MURTHY, Anand S. , RAHHAL-ORABI, Nadia , ZELICK, Nancy M. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/205 , H01L29/66795 , H01L29/66818
摘要： An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，包括：鳍结构，其包括上部和下部，所述上部具有与所述下部的上表面直接接触的底面; 其中（a）下部包括在具有至少2:1的纵横比（深度与宽度）的沟槽中; （b）底面具有底部最大宽度，并且上表面具有大于底部最大宽度的上最大宽度; （c）底面覆盖上表面的中间部分，但不覆盖上表面的侧面部分; 和（d）上部包括上III-V材料，下部包括不同于上III-V材料的下III-V材料。本文描述了其它实施例。

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