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41. 发明申请

WO2004042804A2 CAPACITOR FABRICATION METHODS AND CAPACITOR STRUCTURES INCLUDING NIOBIUM OXIDE 审中-公开
标题翻译：电容器制造方法和电容器结构，包括氧化铌
公开(公告)号：WO2004042804A2
公开(公告)日：2004-05-21
申请号：PCT/US2003/034727
申请日：2003-10-31
申请人： PLANAR SYSTEMS, INC. , AITCHISON, Bradley, J , PAKKALA, Arto , KUOSMANEN, Pekka , HÄRKÖNEN, Kari
发明人： AITCHISON, Bradley, J , PAKKALA, Arto , KUOSMANEN, Pekka , HÄRKÖNEN, Kari
IPC分类号： H01L21/02
CPC分类号： H01L21/02175 , H01L21/02178 , H01L21/022 , H01L21/0228 , H01L21/02362 , H01L21/3142 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L27/10805 , H01L27/10829 , H01L27/1085 , H01L27/10861 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A dielectric structure (304) formed on a substrate (300) using a thin film deposition technique such as atomic layer deposition (ALD) includes at least one layer of current leakage inhibiting dielectric material (310), such as Al 2 O 3 , HfO 2 , or ZrO 2 , for example, in combination with niobium oxide (Nb 2 O 5 ). The Nb 2 O 5 is either incorporated into the dielectric structure as a dopant in a layer of the current leakage inhibiting material (310) or as one or more separate layers (320, 340) in addition to the layer or layers of current leakage inhibiting material (310). The dielectric structure (304) may be used in miniature capacitors for integrated circuit devices such as DRAM devices, for example. In some embodiments, one or more capacitor electrodes (300, 390) are formed around the dielectric structure (304) in the same ALD processing system. One or more of the electrodes (300, 390) may comprise a transition metal nitride, a noble metal, or a noble metal alloy.
摘要翻译：使用诸如原子层沉积（ALD）之类的薄膜沉积技术在衬底（300）上形成的电介质结构（304）包括至少一个电流泄漏抑制电介质材料（310）层，例如Al 2 O 3 3，HfO 2或ZrO 2，例如与氧化铌的组合（铌<子> 2 0 <子> 5 ）。在电流泄漏抑制材料（310）的层中或者作为一个或多个单独的层（320）将Nb 2 O 5或者纳入电介质结构中作为掺杂剂，340）以及电流泄漏抑制材料（310）的层。例如，电介质结构（304）可以用于诸如DRAM器件的集成电路器件的微型电容器。在一些实施例中，在同一ALD处理系统中的电介质结构（304）周围形成一个或多个电容器电极（300,390）。一个或多个电极（300,390）可以包括过渡金属氮化物，贵金属或贵金属合金。

42. 发明申请

WO1986004454A1 CONTROLLED BORON DOPING OF SILICON 审中-公开
标题翻译：有机硅的控制硼
公开(公告)号：WO1986004454A1
公开(公告)日：1986-07-31
申请号：PCT/US1985002501
申请日：1985-12-16
申请人： AMERICAN TELEPHONE & TELEGRAPH COMPANY
发明人： AMERICAN TELEPHONE & TELEGRAPH COMPANY , LIN, Albert, Miin-Ron
IPC分类号： H01L21/225
CPC分类号： H01L29/945 , H01L21/2256 , H01L21/76237 , Y10S438/923
摘要： A technique for doping a silicon body (10) with boron. The surface to be doped is typically a trench sidewall, to be used as a storage capacitor or for isolation. By providing a silicon dioxide diffusion control layer, (20) and a polysilicon source layer (30) that incorporates the boron, well-controlled boron doping over a wide concentration range can be obtained. Control of the doping transfer can be obtained by the choice of ambients, either dry or steam. Furthermore, removal of the silicon dioxide and polysilicon layers following the doping process is facilitated due to the etch selectivity possible between SiO2 and Si. If desired, the layers may remain on the silicon body.

43. 发明申请

WO8603620A3 PROCESS FOR FORMING DIFFUSION REGIONS IN A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：在半导体衬底中形成扩散区的工艺
公开(公告)号：WO8603620A3
公开(公告)日：1986-07-31
申请号：PCT/US8502302
申请日：1985-11-25
申请人： NCR CO
发明人： COLLINS GEORGE JOSEPH , METZ WERNER ADAM JR
IPC分类号： H01L21/76 , H01L21/225 , H01L21/762 , H01L29/94
CPC分类号： H01L21/76237 , H01L21/2255 , H01L29/945
摘要： In a process for forming diffusion regions (12) in a semiconductor substrate (40), trenches (43) are formed in the substrate surface, a doped insulator layer (49) is formed over the substrate surface including the sidewalls (46) and floors (47) of the trenches and an anisotropic etch is utilized to remove the doped insulator material except for sidewall sections (49V) on the trench sidewalls (46). Next, a heating step is effective to drive dopant from the sidewall sections (49V) into the semiconductor substrate (40) thereby forming thin diffusion regions (12) adjacent the trench sidewalls (46). The trenches are then filled with dielectric material (51). The diffusion regions (12) can be utilized as narrow channel stops for CMOS structures in the substrate (40).

44. 发明申请

WO8603620A2 PROCESS FOR FORMING DIFFUSION REGIONS IN A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：在半导体衬底中形成扩散区的工艺
公开(公告)号：WO8603620A2
公开(公告)日：1986-06-19
申请号：PCT/US8502302
申请日：1985-11-25
申请人： NCR CO
发明人： COLLINS GEORGE JOSEPH , METZ WERNER ADAM JR
IPC分类号： H01L21/76 , H01L21/225 , H01L21/762 , H01L29/94
CPC分类号： H01L21/76237 , H01L21/2255 , H01L29/945
摘要： In a process for forming diffusion regions (12) in a semiconductor substrate (40), trenches (43) are formed in the substrate surface, a doped insulator layer (49) is formed over the substrate surface including the sidewalls (46) and floors (47) of the trenches and an anisotropic etch is utilized to remove the doped insulator material except for sidewall sections (49V) on the trench sidewalls (46). Next, a heating step is effective to drive dopant from the sidewall sections (49V) into the semiconductor substrate (40) thereby forming thin diffusion regions (12) adjacent the trench sidewalls (46). The trenches are then filled with dielectric material (51). The diffusion regions (12) can be utilized as narrow channel stops for CMOS structures in the substrate (40).
摘要翻译：在半导体衬底（40）中形成扩散区（12）的工艺中，在衬底表面中形成沟槽（43），在衬底表面上形成掺杂的绝缘体层（49），该衬底表面包括侧壁（46）和层（47）和各向异性蚀刻用于除去在沟槽侧壁（46）上的侧壁部分（49V）之外的掺杂绝缘体材料。接下来，加热步骤有效地将掺杂剂从侧壁部分（49V）驱动到半导体衬底（40）中，从而形成邻近沟槽侧壁（46）的薄的扩散区域（12）。然后用电介质材料（51）填充沟槽。扩散区（12）可以用作衬底（40）中的CMOS结构的窄通道停止点。

45. 发明申请

WO2015047233A1 METHODS OF FORMING BURIED VERTICAL CAPACITORS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成BURIED垂直电容器的方法及其形成的结构
公开(公告)号：WO2015047233A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/061538
申请日：2013-09-25
申请人： INTEL CORPORATION , GASKARAN, Rajashree , JUN, Kimin , MORROW, Patrick
发明人： GASKARAN, Rajashree , JUN, Kimin , MORROW, Patrick
IPC分类号： H01L21/20
CPC分类号： H01L27/10832 , H01L21/84 , H01L27/0629 , H01L27/0688 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L28/20 , H01L28/87 , H01L28/91 , H01L29/945
摘要： Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.
摘要翻译：描述了在器件层下形成无源元件的方法。这些方法和结构可以包括在衬底中形成至少一个无源结构，例如电容器和电阻器结构，其中被动结构垂直地设置在衬底内。绝缘体层形成在无源结构的顶表面上，在绝缘体层上形成器件层，并且形成接触件以将布置在器件层中的器件耦合到至少一个被动结构。

46. 发明申请

WO2013184308A1 DRAM WITH A NANOWIRE ACCESS TRANSISTOR 审中-公开
标题翻译：具有纳米访问晶体管的DRAM
公开(公告)号：WO2013184308A1
公开(公告)日：2013-12-12
申请号：PCT/US2013/041038
申请日：2013-05-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： CHANG, Josephine , SLEIGHT, Jeffrey, W.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10805 , B82Y10/00 , H01L21/84 , H01L27/0207 , H01L27/10873 , H01L27/1203 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/945 , Y10S977/89 , Y10S977/943
摘要： A semiconductor nanowire is formed integrally with a wraparound semiconductor portion (30D) that contacts sidewalls of a conductive cap structure (18) located at an upper portion of a deep trench and contacting an inner electrode (16) of a deep trench capacitor. The semiconductor nanowire (30N) is suspended from above a buried insulator layer (20). A gate dielectric layer (32L) is formed on the surfaces of the semiconductor material structure (30P) including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion (30D) is formed around a center portion of the semiconductor nanowire and gate spacers (52) are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
摘要翻译：半导体纳米线与环绕半导体部分（30D）一体地形成，该环绕半导体部分（30D）接触位于深沟槽的上部并且与深沟槽电容器的内部电极（16）接触的导电盖结构（18）的侧壁。半导体纳米线（30N）从掩埋绝缘体层（20）的上方悬挂。在包括半导体纳米线和环绕半导体部分的半导体材料结构（30P）的表面上形成栅极电介质层（32L）。围绕半导体纳米线的中心部分形成环形栅电极部分（30D），形成栅极间隔物（52）。去除图案化的半导体材料结构的物理曝光部分，并且执行选择性外延和金属化以将半导体纳米线的源极端部连接到导电帽结构。

47. 发明申请

WO2010075052A1 DEEP TRENCH VARACTORS 审中-公开
公开(公告)号：WO2010075052A1
公开(公告)日：2010-07-01
申请号：PCT/US2009/067972
申请日：2009-12-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COLLINS, David, S. , RASSEL, Robert, M. , THOMPSON, Eric
发明人： COLLINS, David, S. , RASSEL, Robert, M. , THOMPSON, Eric
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L27/0805 , H01L27/0808 , H01L29/66181 , H01L29/945
摘要： A deep trench varactor structure (3OA, 4OA, 50) compatible with a deep trench capacitor structure (20, 30B, 40B) and methods of manufacturing the same are provided. A buried plate layer (20) is formed on a second deep trench (HB), while the first trench (1 IA) is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes (4OA, 40B). At least one doped well (50) is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells (50, 60) may be connected in parallel to provide a varactor (30A, 4OA, 50, 60) having complex voltage dependency of capacitance. The buried plate layer and another doped well (52) connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.
摘要翻译：提供了与深沟槽电容器结构（20,30B，40B）兼容的深沟槽变容二极管结构（30A，40A，50）及其制造方法。掩埋板层（20）形成在第二深沟槽（HB）上，而第一沟槽（11A）被保护而不形成任何掩埋的板层。深沟槽的内部填充有导电材料以形成内部电极（40A，40B）。至少一个掺杂阱（50）形成在第一深沟槽的外部和邻接部分上，并且构成至少一个外变容二极管电极。多个掺杂阱（50,60）可以并联连接以提供具有复杂的电容电压依赖性的变容二极管（30A，40A，50,60）。掩埋板层和与其连接的另一个掺杂阱（52）构成形成在第二深沟槽上的线性电容器的外部电极。

48. 发明申请

WO2008042695A2 SEMICONDUCTOR DEVICES CONTAINING NITRIDED HIGH DIELECTRIC CONSTANT FILMS AND METHOD OF FORMING 审中-公开
标题翻译：含有高介电常数膜的半导体器件及其形成方法
公开(公告)号：WO2008042695A2
公开(公告)日：2008-04-10
申请号：PCT/US2007/079681
申请日：2007-09-27
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , CLARK, Robert, D.
发明人： CLARK, Robert, D.
CPC分类号： H01L21/3142 , C23C16/308 , C23C16/45529 , C23C16/45531 , C23C16/45542 , H01L21/28202 , H01L21/3145 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/945
摘要： A semiconductor device containing a substrate (25, 92) and a nitrided high-k film (96) on the substrate (25, 92), and method of forming a nitrided high-k film (96). The nitrided high-k film (96) contains an oxygen-containing film and a nitrogen- containing film that is oxidized through at least a portion of the thickness thereof. The nitrogen-containing film and the oxygen-containing film contain the same one or more metal elements selected from alkaline earth elements, rare earth elements, and Group IVB elements of the Periodic Table. The nitrided high-k film (96) can optionally further contain aluminum, siiicon, or aluminum and silicon. The nitrided high-k film (96) is formed on the substrate (25, 92) by a) depositing a nitrogen-containing film, and b) depositing an oxygen-containing film, wherein steps a) and b) are performed in any order, any number of times, so as to oxidize at least a portion of the thickness of the nitrogen-containing film. According to one embodiment, the method includes forming a nitrided hafnium based high-k film (96).
摘要翻译：在衬底（25,92）上含有衬底（25,92）和氮化高k膜（96）的半导体器件，以及形成氮化高k膜（96）的方法。氮化高k膜（96）含有含氧膜和通过其厚度的至少一部分被氧化的含氮膜。含氮膜和含氧膜含有相同的一种或多种选自碱土金属元素，稀土元素和元素周期表IVB族元素的金属元素。氮化高k膜（96）可以任选地进一步包含铝，硅或铝和硅。氮化的高k膜（96）通过a）沉积含氮膜而形成在基板（25,92）上，b）沉积含氧膜，其中步骤a）和b）以任何方式进行任意次数，以便氧化至少一部分含氮膜的厚度。根据一个实施方案，该方法包括形成氮化铪基高k膜（96）。

49. 发明申请

WO2007005141A1 A SEMICONDUCTOR DEVICE INCLUDING A VERTICAL DECOUPLING CAPACITOR 审中-公开
标题翻译：包括垂直解耦电容器的半导体器件
公开(公告)号：WO2007005141A1
公开(公告)日：2007-01-11
申请号：PCT/US2006/019960
申请日：2006-05-23
申请人： ADVANCED MICRO DEVICES INC. , LEHR, Matthias , FROHBERG, Kai , SCHWAN, Christoph
发明人： LEHR, Matthias , FROHBERG, Kai , SCHWAN, Christoph
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L29/945
摘要： A vertical or three-dimensional non-planar configuration for a decoupling capacitor (240, 340, 440, 540) is provided, which significantly reduces the required die area for capacitors of high charge carrier storage capacity. The non-planar configuration of the decoupling capacitors (240, 340, 440, 540) also provides enhanced pattern uniformity during the highly critical gate patterning process.
摘要翻译：提供了用于去耦电容器（240,340,440,540）的垂直或三维非平面配置，这显着地减少了高电荷载流子存储容量的电容器所需的管芯面积。去耦电容器（240,340,440,540）的非平面配置还在高度关键的栅极图案化工艺期间提供增强的图案均匀性。

50. 发明申请

WO2004102674A1 TRENCH-SPEICHERKONDENSATOR UND VERFAHREN ZU DESSEN HERSTELLUNG 审中-公开
标题翻译： TRENCH存储器用电容器和方法及其
公开(公告)号：WO2004102674A1
公开(公告)日：2004-11-25
申请号：PCT/DE2004/001003
申请日：2004-05-13
申请人： INFINEON TECHNOLOGIES AG , SEIDL, Harald , MANGER, Dirk , GOLDBACH, Matthias , BIRNER, Albert , SLESAZECK, Stefan
发明人： SEIDL, Harald , MANGER, Dirk , GOLDBACH, Matthias , BIRNER, Albert , SLESAZECK, Stefan
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/945
摘要： Die Erfindung betrifft einen Trench-Speicherkondensator und ein Verfahren zu dessen Herstellung. Bei diesem Speicherkondensator ist die Buried-Plate (3) durch eine dotierte Siliziumschicht (8) bis über die Collar-Isolierschicht (4) verlängert. Die Leiterschicht (8) wird bevorzugt auf eine "vergrabene" Collar-Isolierschicht aufgebracht und mit Hilfe einer durch ALD hergestellten Schutzschicht (9) maskiert. In einem anderen Ausführungsbeispiel besteht die Leiterschicht (18) aus amorphem Silizium, welches in einem unteren Trenchbereich (12) als HSG-Schicht (18') verwendet wird.
摘要翻译：本发明涉及一种沟槽存储电容器和用于其生产的方法。在该存储电容器中的掩埋极板（3）是由掺杂的硅层延伸（8），以在绝缘卡圈（4）。导体层（8）优选在衣领绝缘层“掩埋”沉积和掩蔽通过ALD（9）中产生的保护层。在另一个实施例中，导体层（18）由非晶硅制成，这是在比HSG层（18“）的下部槽区（12）中使用的。

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