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    • 48. 发明申请
    • PIEZOELECTRIC COUPLED COMPONENT INTEGRATED DEVICES
    • 压电耦合器件集成器件
    • WO2003017373A2
    • 2003-02-27
    • PCT/US2002/025342
    • 2002-08-09
    • MOTOROLA, INC. A CORPORATION OF THE STATE OF DELAWARE
    • HIGGINS, JR., Robert, J.STENGEL, Robert, E.
    • H01L27/20
    • H01L21/02521H01L21/02381H01L21/02439H01L21/02488H01L21/02505H01L27/20H01L41/0815H01L41/1873H01L41/319H03H9/02566H03H9/02574
    • High quality layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22, 2615) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24,2610) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating bufferlayer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The use of monocrystalline piezoelectric material as an overlying layer (2605) is disclosed to facilitate the fabrication of on-chip high frequency communications devices such as microwave SAW devices with direct interface to high speed semiconductor devices in the integrated circuit.
    • 通过形成用于生长单晶层的柔性衬底,可以在单晶衬底(22,2615)(例如大硅晶片)上生长高质量的单晶材料层(26)。 适应缓冲层(24,2610)包括由硅氧化物的非晶界面层与硅晶片隔开的单晶氧化物层。 无定形界面层(28)消除应变并允许高质量单晶氧化物容纳缓冲层的生长。 适应缓冲层与下面的硅晶片和上面的单晶材料层晶格匹配。 适应缓冲层和下面的硅衬底之间的任何晶格失配都由无定形界面层来处理。 另外,柔性衬底的形成可以包括利用表面活性剂增强外延,单晶硅在单晶氧化物上的外延生长以及Zintl相材料的外延生长。 公开了使用单晶压电材料作为上覆层(2605),以便于制造片上高频通信器件,例如与集成电路中的高速半导体器件直接接口的微波SAW器件。
    • 49. 发明申请
    • SEMICONDUCTOR APPARATUS
    • WO2003012861A1
    • 2003-02-13
    • PCT/US2002/014463
    • 2002-05-08
    • MOTOROLA, INC. A CORPORATION OF THE STATE OF DELAWARE
    • STENGEL, Robert, E.HIGGINS, Jr., Robert, J.
    • H01L21/8258
    • H01L27/0605H01L21/8258H01L27/0688
    • A semiconductor apparatus for effecting a plurality of functions involving high frequency signals and low frequency signals includes: (a) at least one first circuit section implemented in at least one first semiconductor material; and (b) at least one second circuit section implemented in at least one second semiconductor material. The at least one second semiconductor material exhibits lower noise generating characteristics than the at least one first semiconductor material at the low frequency signals. The at least one first circuit section and the at least one second circuit section are implemented in an integrated circuit construction. Preferably the integrated circuit construction is a monolithic configuration. Preferably the at least one first semiconductor material includes gallium arsenide. Preferably the at least one second semiconductor material includes silicon.
    • 用于实现涉及高频信号和低频信号的多个功能的半导体装置包括:(a)至少一个第一电路部分,其实现在至少一个第一半导体材料中; 和(b)在至少一个第二半导体材料中实现的至少一个第二电路部分。 所述至少一个第二半导体材料在所述低频信号下表现出比所述至少一个第一半导体材料更低的噪声产生特性。 所述至少一个第一电路部分和所述至少一个第二电路部分以集成电路结构实现。 优选地,集成电路结构是单片结构。 优选地,至少一个第一半导体材料包括砷化镓。 优选地,至少一个第二半导体材料包括硅。
    • 50. 发明申请
    • OPTICAL WAVEGUIDE TRENCHES IN COMPOSITE INTEGRATED CIRCUITS
    • 复合集成电路中的光波导
    • WO2003009024A2
    • 2003-01-30
    • PCT/US2002/014363
    • 2002-05-06
    • MOTOROLA, INC. A CORPORATION OF THE STATE OF DELAWARE
    • TALIN, Albert, A.BARENBURG FOLEY, Barbara
    • G02B6/12
    • G02B6/132G02B6/12004G02B6/122G02B6/43G02B2006/12061G02B2006/1215
    • High quality epitaxial layers of compound semiconductor materials (26) can be grown overlying large silicon wafers(22) by first growing an accommodating buffer layer (24) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between theaccommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Trenches (1038,1042,1046) in composite integrated circuits (1034) are provided that may be used for electrical isolation and strain relief. The trenches (1050,1052,1054) may also be implemented as optical waveguides to carry optical signals on- or off-chip.
    • 通过首先在硅晶片上生长容纳缓冲层(24),可以将复合半导体材料(26)的高质量外延层生长成覆盖在大的硅晶片(22)上。 容纳缓冲层是通过氧化硅的非晶界面层(28)与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶化合物半导体层晶格匹配。 通过无定形界面层处理适配缓冲层和底层硅衬底之间的任何晶格失配。 提供复合集成电路(1034)中的沟槽(1038,1042,1046),其可用于电隔离和应变消除。 沟槽(1050,1052,1054)也可以实现为光波导,以承载芯片上或芯片外的光信号。