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31. 发明申请

WO2014102800A1 METHOD AND DEVICE FOR RELIABLE STORAGE IN NOR FLASH MEMORY 审中-公开
标题翻译：在闪存存储器中可靠存储的方法和装置
公开(公告)号：WO2014102800A1
公开(公告)日：2014-07-03
申请号：PCT/IL2013/051087
申请日：2013-12-30
申请人： RAMOT AT TEL-AVIV UNIVERSITY LTD.
发明人： LITSYN, Simon
IPC分类号： G06F11/08 , G11C11/56 , H03M13/03
CPC分类号： H03M13/251 , G06F11/1072 , G11C11/5642
摘要： A method and device for securely storing and reading out data in a flash memory device using multi-level voltage cells uses redundancy based error correction to correct the multi-bit voltage level readings. A number of voltage levels per cell is provided which is higher (typically by one or two) than the number needed for the data to be stored. The resulting redundancy is used to correct the cell readings, for example by correcting the weakest cell level reading in a readout vector until an allowable readout vector is achieved.
摘要翻译：用于使用多电平电压单元安全地存储和读出闪速存储器件中的数据的方法和装置使用基于冗余的纠错来校正多位电压电平读数。提供每个单元的多个电压电平，其高于（通常为一个或两个）比要存储的数据所需的数量。所得到的冗余用于校正单元读数，例如通过校正读出矢量中最弱的单元电平读数，直到达到允许的读出矢量。

32. 发明申请

WO2014052936A1 AUTOMATIC SAFETY LOGIC INSERTION 审中-公开
标题翻译：自动安全逻辑插件
公开(公告)号：WO2014052936A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/062486
申请日：2013-09-27
申请人： ARTERIS SAS , MARTIN, Philippe , BOUTILLIER, Boris , PROUJANSKY-BELL, Jonah , LELOUP, Xavier
发明人： MARTIN, Philippe , BOUTILLIER, Boris , PROUJANSKY-BELL, Jonah , LELOUP, Xavier
IPC分类号： G06F11/08 , G06F11/10
CPC分类号： G06F17/505 , G06F11/10 , G06F2217/70
摘要： A method is disclosed for configurable insertion of safety in library-based designs. The invention can automatically harden the design according to a particular safety goal, without having to modify the original design description.
摘要翻译：公开了一种用于在基于库的设计中可配置地插入安全性的方法。本发明可以根据特定的安全目标自动硬化设计，而无需修改原始设计描述。

33. 发明申请

WO2014051625A1 DYNAMICALLY SELECTING BETWEEN MEMORY ERROR DETECTION AND MEMORY ERROR CORRECTION 审中-公开
标题翻译：在存储器错误检测和存储器错误校正之间动态选择
公开(公告)号：WO2014051625A1
公开(公告)日：2014-04-03
申请号：PCT/US2012/058056
申请日：2012-09-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： MOGUL, Jeffrey Clifford , MURALIMANOHAR, Naveen , SHAH, Mehul A. , ANDERSON, Eric A.
IPC分类号： G11C29/42 , G06F11/08
CPC分类号： G06F11/073 , G06F11/0763 , G06F11/0793 , G06F11/1048 , G11C2029/0411
摘要： Example methods, systems, and apparatus to dynamically select between memory error detection and memory error correction are disclosed herein. An example system includes a buffer to store a flag settable to a first value to indicate that a memory page is to store error protection information to detect but not correct errors in the memory page. The flag is settable to a second value to indicate that the error protection information is to detect and correct errors for the memory page. The example system includes a memory controller to receive a request based on the flag to enable error detection without correction for the memory page when the flag is set to the first value, and to enable error detection and correction for the memory page when the flag is set to the second value.
摘要翻译：本文公开了在存储器错误检测和存储器错误校正之间动态选择的示例性方法，系统和装置。一个示例系统包括一个缓冲器，用于存储可设置到第一值的标志，以指示存储器页面存储错误保护信息以检测存储器页面中的错误，而不是错误。该标志可设置为第二个值，以指示错误保护信息是检测和纠正存储器页面的错误。示例系统包括存储器控制器，用于当标志被设置为第一值时，基于该标志来接收请求以启用错误检测而无需对存储器页进行校正，并且当该标志为标志位时，允许存储器页的错误检测和校正设置为第二个值。

34. 发明申请

WO2014051550A1 NOTIFICATION OF ADDRESS RANGE INCLUDING NON-CORRECTABLE ERROR 审中-公开
标题翻译：通知地址范围包括非正确性错误
公开(公告)号：WO2014051550A1
公开(公告)日：2014-04-03
申请号：PCT/US2012/057107
申请日：2012-09-25
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： WALTON, Andrew, Christopher
IPC分类号： G06F11/08 , G06F12/16
CPC分类号： G06F11/0793 , G06F11/073 , G06F11/1048 , G06F12/0646 , G06F2212/1032
摘要： Techniques are provided for recovering from non-correctable memory errors. A memory location may be accessed. It may be determined that the memory location contains a non-correctable error. A range of addresses associated with the memory location may be determined. Corrective action may be taken on the entire range of addresses to identify other addresses within the range of addresses that contain non-correctable memory errors.
摘要翻译：提供了从不可校正的内存错误中恢复的技术。可以访问存储器位置。可以确定存储器位置包含不可校正的错误。可以确定与存储器位置相关联的一系列地址。可以在整个地址范围内采取纠正措施，以识别包含不可校正内存错误的地址范围内的其他地址。

35. 发明申请

WO2013156823A1 INFORMATION PROCESSING DEVICE AND METHOD FOR PROTECTING DATA IN A CALL STACK 审中-公开
标题翻译：信息处理装置和用于保护呼叫堆栈中的数据的方法
公开(公告)号：WO2013156823A1
公开(公告)日：2013-10-24
申请号：PCT/IB2012/051998
申请日：2012-04-20
申请人： FREESCALE SEMICONDUCTOR, INC. , POROSANU, Alexandru
发明人： POROSANU, Alexandru
IPC分类号： G06F9/06 , G06F9/44 , G06F11/08
CPC分类号： G06F9/44 , G06F9/06 , G06F9/4482 , G06F11/1004
摘要： An information processing device (10) comprises a control unit (12), a hash unit (16), and a comparison unit (18). The control unit (12) is arranged to run a program and to store at least flow control information of the program in a call stack. The hash unit (16) is arranged to generate a first hash value by applying a hash function to selected data in response to a first context change of the program, the selected data comprising at least one or more selected items of the call stack, the first context change comprising a termination or interruption of a first process or thread of the program. The control unit (12) is further arranged to start or resume a second process or thread of the program only when the hash unit has generated the first hash value. The hash unit (16) is further arranged to generate a second hash value by re-applying the hash function to the selected data in response to a second context change, the second context change comprising a termination or interruption of the second process or thread. The comparison unit (18) is arranged to determine whether the first hash value and the second hash value are identical.
摘要翻译：信息处理装置（10）包括控制单元（12），散列单元（16）和比较单元（18）。控制单元（12）被布置成运行程序并且至少存储程序在调用堆栈中的流控制信息。哈希单元（16）被布置成通过响应于程序的第一上下文改变而将哈希函数应用于所选择的数据来生成第一哈希值，所选择的数据包括呼叫栈的至少一个或多个所选项，第一上下文改变包括程序的第一进程或线程的终止或中断。控制单元（12）还被布置成仅当散列单元已经产生了第一哈希值时才启动或恢复程序的第二进程或线程。哈希单元（16）还被布置为通过响应于第二上下文改变将哈希函数重新应用于所选择的数据来生成第二哈希值，第二上下文改变包括第二进程或线程的终止或中断。比较单元（18）被布置为确定第一哈希值和第二哈希值是否相同。

36. 发明申请

WO2013103951A1 HOST SIDE IMPLEMENTATION FOR HID I2C DATA BUS 审中-公开
标题翻译： HID I2C数据总线的主机端实现
公开(公告)号：WO2013103951A1
公开(公告)日：2013-07-11
申请号：PCT/US2013/020501
申请日：2013-01-07
申请人： MICROSOFT CORPORATION
发明人： BHESANIA, Firdosh K. , AIYAR, Arvind R. , DA, Di
IPC分类号： G06F13/38 , G06F13/14 , G06F11/08
CPC分类号： G06F13/28 , G06F9/4411 , Y02D10/14
摘要： In embodiments of host side implementation for HID I 2 C data bus, a computing system includes a human interface device (HID) software stack that implements device software, such as for embedded devices, that interfaces the computing system to a peripheral device via HID over I 2 C. An HID I 2 C driver interfaces the HID software stack with the peripheral devices that each include an HID I 2 C interface to a device that communicates data in the computing system via an I 2 C data bus. The HID I 2 C driver is compatible and interfaces with I 2 C controller drivers and GPIO controller drivers of the devices, where the I 2 C controller drivers and the GPIO controller drivers may each have a different implementation configuration.
摘要翻译：在HID I2C数据总线的主机实现实施例中，计算系统包括实现诸如用于嵌入式设备的设备软件的人机界面设备（HID）软件栈，其通过I2C上的HID将计算系统连接到外围设备。 HID I2C驱动器将HID软件堆栈与包含HID I2C接口的外围设备连接到通过I2C数据总线在计算系统中传送数据的设备。 HID I2C驱动器兼容并与设备的I2C控制器驱动程序和GPIO控制器驱动程序接口，其中I2C控制器驱动程序和GPIO控制器驱动程序可能各自具有不同的实现配置。

37. 发明申请

WO2013101123A1 RECOVERING FROM ERRORS USING IMPLICIT REDUNDANCY 审中-公开
标题翻译：从误差恢复使用隐含的冗余
公开(公告)号：WO2013101123A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067970
申请日：2011-12-29
申请人： INTEL CORPORATION , VERA, Xavier , MONCHIERO, Matteo , CASADO, Javier, Carretero , HERRERO, Enric , RAMIREZ, Tanausu
发明人： VERA, Xavier , MONCHIERO, Matteo , CASADO, Javier, Carretero , HERRERO, Enric , RAMIREZ, Tanausu
IPC分类号： G06F11/08 , G06F12/16 , G06F15/80
CPC分类号： G06F12/0822 , G06F11/00 , G06F11/08 , G06F11/1666 , G06F11/20 , G06F12/0806 , G06F12/0815 , G06F12/0817 , G06F12/12 , G06F2212/1024 , G06F2212/1028 , G06F2212/1044 , Y02D10/13
摘要： Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.
摘要翻译：本文公开的一些实现方式提供了通过存储在高速缓存目录中的信息来恢复存储在由多个处理器共享的存储器中的数据的技术和装置。处理器的核心可以启动对位于核心可访问的第一高速缓存中的特定数据的访问（例如，读或写）。响应于检测到与访问特定数据相关联的错误，可以识别包括特定数据的处理器中的位置，并且可以将特定数据从该位置复制到第一高速缓存。

38. 发明申请

WO2013062585A1 METHOD AND SYSTEM FOR SINGLE POINT OF FAILURE ANALYSIS AND REMEDIATION 审中-公开
标题翻译：单点故障分析与补救的方法与系统
公开(公告)号：WO2013062585A1
公开(公告)日：2013-05-02
申请号：PCT/US2011/058353
申请日：2011-10-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , KRAMPEN, Stefan , WOLF, Kay
发明人： KRAMPEN, Stefan , WOLF, Kay
IPC分类号： G06F11/08 , G06F9/44 , G06F3/14
CPC分类号： G06F11/079 , G06F11/2257
摘要： Embodiments of the present invention disclose a method and system for single point of failure analysis (SPOF) and remediation. According to one embodiment, a SPOF analysis is performed based on component configuration information associated with a plurality of system components. Based on the SPOF analysis, at least one SPOF component is identified. In addition, remediation information for the identified SPOF is computed based on the component configuration information. The result of the SPOF analysis and the remediation information are then displayed to an operating user.
摘要翻译：本发明的实施例公开了单点故障分析（SPOF）和补救的方法和系统。根据一个实施例，基于与多个系统组件相关联的组件配置信息执行SPOF分析。基于SPOF分析，识别至少一个SPOF组件。此外，基于组件配置信息计算所识别的SPOF的补救信息。然后将SPOF分析和修复信息的结果显示给操作用户。

39. 发明申请

WO2013062204A1 에러 정정 코드의 저장을 위한 플래시 메모리 제어장치 및 방법 审中-公开
标题翻译：用于控制用于存储错误校正码的闪速存储器的设备和方法
公开(公告)号：WO2013062204A1
公开(公告)日：2013-05-02
申请号：PCT/KR2012/004566
申请日：2012-06-08
申请人： 한양대학교 산학협력단 , 송용호 , 정상혁 , 정재형
发明人： 송용호 , 정상혁 , 정재형
IPC分类号： G06F12/00 , G06F11/08
CPC分类号： G06F11/1044 , G06F11/108
摘要： 에러 정정 코드의 저장을 위한 플래시 메모리 제어장치 및 방법이 개시된다. 페이지 단위로 데이터가 저장되며, 상기 페이지가 사전에 설정된 개수의 섹터로 구성된 플래시 메모리를 제어하기 위하여, 호스트 인터페이스부는 호스트와 제어신호 및 데이터를 송수신하며, 메모리 인터페이스부는 호스트로부터 쓰기 제어신호와 함께 수신된 쓰기 대상 데이터 및 쓰기 대상 데이터에 대응하여 생성된 에러 정정 코드를 플래시 메모리의 페이지에 저장하되, 쓰기 대상 데이터가 저장되는 데이터 영역에 해당하는 복수의 섹터 중 사전에 설정된 개수의 섹터에 대응하는 영역을 에러 정정 코드의 저장영역으로 추가 할당한다.
摘要翻译：本发明涉及一种用于控制用于存储纠错码的闪速存储器的装置和方法。数据以页面单位存储，主机接口从/向主机发送/发送控制信号和数据，使得控制页面包括预设数量的扇区的闪存，并且存储器接口单元将数据存储为与来自主机的写入控制信号一起被接收的写入以及响应于要写入的数据而产生的纠错码在闪速存储器的页面中，其中对应于多个扇区中的预设数量的扇区的区域对应于要写入数据的数据区域的扇区被进一步分配为纠错码的存储区域。

40. 发明申请

WO2013039535A1 QUERYING AND REPAIRING DATA 审中-公开
标题翻译：查询和修复数据
公开(公告)号：WO2013039535A1
公开(公告)日：2013-03-21
申请号：PCT/US2011/055832
申请日：2011-10-11
申请人： MICROSOFT CORPORATION
发明人： LEE, Chesong , MILLER, Thomas J. , CHRISTIANSEN, Neal R. , GARSON, Matthew S.
IPC分类号： G06F11/08
CPC分类号： G06F11/1415 , G06F11/1004 , G06F11/1076 , G06F11/1402 , G06F11/1662 , G06F11/2094 , G06F2211/1088
摘要： Aspects of the subject matter described herein relate to querying and repairing data. In aspects, a component may detect that data on storage has become corrupted. In response, the component may request data from one or more redundant copies of the data and may determine which of the redundant copies, if any, are not corrupted. If a non- corrupted copy is found, the component may send a request that the corrupted data be repaired and may identify the non-corrupted copy to use to repair the corrupted data.
摘要翻译：这里描述的主题的各方面涉及查询和修复数据。在各方面，组件可以检测到存储上的数据已经被损坏。作为响应，组件可以从数据的一个或多个冗余副本请求数据并且可以确定哪些冗余副本（如果有的话）没有被损坏。如果发现未损坏的副本，组件可以发送请求，修复损坏的数据，并可以识别未损坏的副本以用于修复损坏的数据。

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