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31. 发明申请

WO2004036754A3 ADAPTIVE MULTI-BIT DELTA AND SIGMA-DELTA MODULATION 审中-公开
标题翻译：自适应多位DELTA和SIGMA-DELTA调制
公开(公告)号：WO2004036754A3
公开(公告)日：2004-06-24
申请号：PCT/US0332835
申请日：2003-10-15
申请人： UNIV CALIFORNIA , ALDAJANI MANSOUR A , SAYED ALI H
发明人： ALDAJANI MANSOUR A , SAYED ALI H
IPC分类号： H04L25/49 , H03M3/00 , H03M7/30 , H03M7/34 , H04B14/06
CPC分类号： H04L25/4927
摘要： An adaptive multi-bit delta and sigma-delta modulation (10) and demodulation technique, wherein a one-bit modulator generates a binary output signal from an analog input signal and a multi-bit adapter (24) for generating a scaling signal for scaling a step-size of the sigma-delta modulator.
摘要翻译：一种自适应多位增量和Σ-Δ调制（10）和解调技术，其中一位调制器从模拟输入信号产生二进制输出信号，并产生用于产生缩放信号的多位适配器（24） Σ-Δ调制器的步长。

32. 发明申请

WO01086638A3 METHOD AND SYSTEM FOR AUDIO COMPRESSION AND DISTRIBUTION 审中-公开
标题翻译：用于音频压缩和分配的方法和系统
公开(公告)号：WO01086638A3
公开(公告)日：2002-04-04
申请号：PCT/CA2001/000631
申请日：2001-05-09
IPC分类号： G10L19/02 , G10L19/04 , H04B1/66 , H03M3/04 , H04B14/06
CPC分类号： G10L19/04 , G10L19/0204 , H04B1/66
摘要： Typical audio compression/decompression systems require a software application or browser plugin on the end user's computer because their decompression requires a great deal of processing, particularly of series of trigonometric functions. The invention provides a method and system in which audio data is decompressed using simple linear operations, which allows music quality audio to be decompressed in real time. This also allows the decompression to be performed in a Java environment, so executable audio applets can be posted on Web sites, and be universally accessible.
摘要翻译：典型的音频压缩/解压缩系统需要在最终用户计算机上使用软件应用程序或浏览器插件，因为它们的解压缩需要大量的处理，特别是一系列的三角函数。本发明提供了一种方法和系统，其中使用简单的线性操作来解压缩音频数据，这允许音乐质量的音频被实时解压缩。这还允许在Java环境中执行解压缩，因此可执行的音频小程序可以在网站上发布，并且可以普遍访问。

33. 发明申请

WO01052411A2 GENERATING COEFFICIENTS FOR A PREDICTION FILTER IN AN ENCODER 审中-公开
标题翻译：一种CODE中预测滤波器系数的生成
公开(公告)号：WO01052411A2
公开(公告)日：2001-07-19
申请号：PCT/EP2000/013223
申请日：2000-12-27
IPC分类号： G10L19/02 , G10L19/06 , H03H21/00 , H03M7/38 , H04B14/06
CPC分类号： H03H21/0012
摘要： A transmitter is disclosed for transmitting a transmission signal via a transmission medium. The transmitter derives a prediction signal from the digital information signal in dependence on an array of prediction filter coefficients. The array of prediction filter coefficients is obtained by smoothing a first array of coefficients. Said first array of coefficients is generated in response to the digital information signal. A residual signal is obtained by combination of the digital information signal and the prediction signal. The residual signal is encoded so as to obtain an encoded signal. The encoded signal is transmitted via the transmission medium.
摘要翻译：本发明涉及用于经由传输介质传输传输信号的传输器。发射机基于一组预测滤波器系数从数字信息信号中提取预测信号。这些系数的集合通过平滑第一组系数而获得。所述第一组系数是响应于数字信息信号而产生的。通过组合数字信息信号和预测信号获得残差信号。残差信号被编码以获得编码信号。编码信号通过传输介质传输。

34. 发明申请

WO01037461A1 METHOD AND APPARATUS FOR GENERATING AN RF SIGNAL 审中-公开
标题翻译：用于生成RF信号的方法和装置
公开(公告)号：WO01037461A1
公开(公告)日：2001-05-25
申请号：PCT/SE2000/002280
申请日：2000-11-20
IPC分类号： H03F3/217 , H03M3/00 , H04B1/04 , H04B14/06 , H04L27/00
CPC分类号： H03F3/2178 , H03F3/24 , H03F2200/331 , H04B2001/0408 , H04B2001/0491
摘要： To generate a high-power modulated radio frequency (RF) signal (SOUT) from an input low or medium frequency information signal (SIN) the information signal is pulse-shaped in a quantifier (108) to form a digital signal (SD) having discrete signal values. The digital signal is processed in a switching unit (106) comprising switches (SW1, SW2, ..., SWM) for each signal value, radio frequency wave generators (210) for each switch generating carrier waves of radio frequency, and control circuits (216) for each switch to control the opening and closing thereof. When a switch is closed, its associated generator is connected to the output line of the switching unit, and when it is opened, the generator is disconnected therefrom. In the switching unit a switched radio frequency signal (SSW) carrying the information of the input signal is formed by opening and closing the switches when the digital signal adopts or does not adopt respectively the signal value associated with the respective switch. The switching is thus controlled by the signal values of the digital signal. The switched signal on the output line of the switching unit is filtered by a filter (208) for achieving the high-power modulated RF signal (SOUT).
摘要翻译：为了从输入低或中频信息信号（SIN）产生高功率调制射频（RF）信号（SOUT），信息信号在量化器（108）中被脉冲形成以形成数字信号（SD），其具有离散信号值。数字信号在包括用于每个信号值的开关（SW1，SW2，...，SWM）的开关单元（106）中被处理，用于产生无线电频率的载波的每个开关的射频发生器（210）和控制电路（216），用于控制其开启和关闭。当开关闭合时，其相关联的发电机连接到开关单元的输出线，当其断开时，发电机与其断开连接。在开关单元中，当数字信号采用或不分别采用与各个开关相关联的信号值时，通过打开和关闭开关来形成承载输入信号的信息的开关射频信号（SSW）。因此，开关由数字信号的信号值控制。开关单元的输出线上的开关信号由用于实现高功率调制RF信号（SOUT）的滤波器（208）滤波。

35. 发明申请

WO01010035A1 VARIABLE ORDER SIGMA - DELTA MODULATOR 审中-公开
标题翻译： VARIABLE ORDER SIGMA - DELTA调制器
公开(公告)号：WO01010035A1
公开(公告)日：2001-02-08
申请号：PCT/EP2000/006808
申请日：2000-07-17
IPC分类号： H03M3/04 , H03M3/02 , H04B14/06
CPC分类号： H03M3/394 , H03M3/454
摘要： A Sigma-Delta modulator(10) comprises a signal input (34) coupled to a forward filter comprising a series connection of a plurality of N summing stages (28, 30, 32), where N is an integer of at least 2, alternating with a corresponding plurality of integrating stages (40, 42, 44) and an analogue to digital converter (ADC) (18) having an input coupled to an output of the Nth integrating stage (44) and an output. A feedback filter comprises a feedback coupling from the output of the ADC (18) to a digital to analogue converter (DAC) (26) which is coupled to an input of each of the summing stages by way of respective weights (46, 48, 50). Control means (66) including switching means (58, 64) are provided for changing the order of the modulator. To reduce the order and increase the bandwidth, the control means by-passes the first (40) of the integrating stages and uses the second (42) of the integrating stages as a first of the integrating stages and vice versa to increase the order and decrease the bandwidth.
摘要翻译： Σ-Δ调制器（10）包括耦合到正向滤波器的信号输入（34），该正向滤波器包括多个N个加法级（28,30,32）的串联连接，其中N是至少为2的整数，交替具有对应的多个积分级（40,42,44）和模数转换器（ADC）（18），其具有耦合到第N个积分级（44）的输出的输入和输出。反馈滤波器包括从ADC（18）的输出到数模转换器（DAC）（26）的反馈耦合，其通过相应的权重（46,48,48）耦合到每个求和级的输入， 50）。提供包括切换装置（58,64）的控制装置（66），用于改变调制器的次序。为了减小顺序并增加带宽，控制装置绕过积分级的第一（40），并且使用积分级的第二（42）作为积分级的第一级，反之亦然，以增加顺序和降低带宽。

36. 发明申请

WO00008764A1 DIGITAL RECEPTION WITH RADIO FREQUENCY SAMPLING 审中-公开
标题翻译：数字接收无线电频率采样
公开(公告)号：WO00008764A1
公开(公告)日：2000-02-17
申请号：PCT/EP1999/005005
申请日：1999-07-15
IPC分类号： H03D3/00 , H03M3/02 , H04B14/06 , H04L27/14 , H04L27/233
CPC分类号： H03D3/007 , H03M3/40 , H03M3/43 , H04L27/2332
摘要： A radio frequency signal is received by using a sigma-delta analog-to-digital converter to sample the radio frequency signal at a sampling rate and to generate therefrom 1-bit digital samples representing a digital intermediate frequency signal. The intermediate frequency signal is demodulated to generate in-phase and quadrature samples. Demodulation may be performed by generating a first mixed signal by combining the 1-bit digital samples representing the intermediate frequency signal with a first sequence representing a cosine mixing signal; generating a second mixed signal by combining the 1-bit digital samples representing the intermediate frequency signal with a second sequence representing a sine mixing signal; and decimating the first and second mixed signals to generate the in-phase and quadrature samples. In alternative embodiments, the intermediate frequency signal is directly converted to in-phase and quadrature signals by using bandpass decimation filtering to subsample two time-shifted sequences of the intermediate frequency. In another alternative, the sigma-delta analog-to-digital converter uses subsampling to convert the radio frequency signal to a first intermediate frequency, and a decimation filter is used to further convert the signal to a second intermediate frequency. An IQ demodulator then reconstructs the in-phase and quadrature signals from the second intermediate frequency signal.
摘要翻译：通过使用Σ-Δ模拟 - 数字转换器以采样率对射频信号进行采样并从其生成表示数字中频信号的1位数字采样来接收射频信号。解调中频信号以产生同相和正交采样。可以通过将表示中频信号的1比特数字样本与代表余弦混合信号的第一序列组合来产生第一混合信号来进行解调; 通过组合表示中频信号的1比特数字样本和表示正弦混合信号的第二序列来产生第二混合信号; 并抽取第一和第二混合信号以产生同相和正交采样。在替代实施例中，通过使用带通抽取滤波来将中频信号直接转换成同相和正交信号，以对两个中频频率的时移序列进行二次采样。在另一替代方案中，Σ-Δ模数转换器使用二次采样将射频信号转换为第一中频，并且使用抽取滤波器来进一步将信号转换为第二中频。然后，IQ解调器从第二中频信号重建同相和正交信号。

37. 发明申请

WO00001072A1 SYSTEM FOR GENERATING AN ACCURATE LOW-NOISE PERIODIC SIGNAL 审中-公开
标题翻译：用于产生精确低噪声周期信号的系统
公开(公告)号：WO00001072A1
公开(公告)日：2000-01-06
申请号：PCT/US1999/014655
申请日：1999-06-29
IPC分类号： H03M3/02 , H03L7/08 , H03L7/18 , H03L7/197 , H04B14/06 , G06F1/02
CPC分类号： H03L7/1806
摘要： In the illustrative embodiment, the inventive system includes a low-bit digital-to-analog converter (68) for converting a first signal at a reference frequency to a digital signal. A delta-sigma converter is included for suppressing noise in the digital signal within the predetermined range of the reference frequency and providing a noise-shaped signal in response thereto. A bandpass filter (72) filters out the out-of-band noise and provides an accurate periodic signal which lacks glitch noise. In a particular embodiment, the inventive system further includes a direct digital synthesizer (42) for providing the first signal at the first frequency and the accurate reference periodic signal is supplied as reference signal to a phase-locked loop (50).
摘要翻译：在说明性实施例中，本发明的系统包括用于将参考频率的第一信号转换为数字信号的低位数模转换器（68）。包括Δ-Σ转换器，用于抑制在参考频率的预定范围内的数字信号中的噪声，并响应于此提供噪声形状的信号。带通滤波器（72）滤除带外噪声，并提供缺少毛刺噪声的精确周期信号。在特定实施例中，本发明的系统还包括用于以第一频率提供第一信号的直接数字合成器（42），并将准确的参考周期信号作为参考信号提供给锁相环（50）。

38. 发明申请

WO99020004A1 SIGNAL PROCESSING METHOD AND DEVICE 审中-公开
标题翻译：信号处理方法和装置
公开(公告)号：WO99020004A1
公开(公告)日：1999-04-22
申请号：PCT/US1998/017743
申请日：1998-08-26
IPC分类号： H03M3/02 , H03M7/00 , H03M7/36 , H04B14/06
CPC分类号： H03M3/458 , H03M7/3028 , H03M7/304
摘要： The invention relates to digital signal processing and specificly to level control of a pulse density modulated (PDM) signal generated by a sigma-delta modulator. A single-bit pulse density modulated PDM signal is generated by a first sigma-delta modulator (2) being an analog modulator, for instance. Level control is performed by multiplying the single-bit pulse density modulated PDM signal by a multibit multiplier (300) to obtain a multibit number stream, which is reconverted into a single-bit PDM signal by a second digital sigma-delta modulator (4). In accordance with the invention, the performance of the second sigma-delta modulator (4) is better than that of the first sigma-delta modulator (2), as to the signal-to-noise ratio. Thus, the most significant factor in the total signal-to-noise ratio (SNR) is the noise level of the first sigma-delta modulator (2), by which the PDM signal was originally generated. In the subsequent second sigma-delta modulator (4), the PDM signal can then be attenuated as much as is the difference between the SNR performances of the modulators without any decrease in the total signal-to-noise ratio. A relative amplification of the PDM signal is provided in this manner.
摘要翻译：本发明涉及数字信号处理，特别涉及由Σ-Δ调制器产生的脉冲密度调制（PDM）信号的电平控制。例如，通过作为模拟调制器的第一Σ-Δ调制器（2）产生单位脉冲密度调制PDM信号。通过将单位脉冲浓度调制的PDM信号乘以多位乘法器（300）来执行电平控制以获得多位数流，其由第二数字Σ-Δ调制器（4）再转换为单位PDM信号，。根据本发明，关于信噪比，第二Σ-Δ调制器（4）的性能优于第一Σ-Δ调制器（2）的性能。因此，总信噪比（SNR）中最重要的因素是最初产生PDM信号的第一Σ-Δ调制器（2）的噪声电平。在随后的第二Σ-Δ调制器（4）中，PDM信号可以像调制器的SNR性能之间的差异一样被衰减，而不会降低总的信噪比。以这种方式提供PDM信号的相对放大。

39. 发明申请

WO1990004891A1 VOICE SIGNAL DEMODULATION CIRCUIT 审中-公开
标题翻译：语音信号解调电路
公开(公告)号：WO1990004891A1
公开(公告)日：1990-05-03
申请号：PCT/JP1989001089
申请日：1989-10-24
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , NIPPON HOSO KYOKAI , MIYOSHI, Toshihiro , OKUMURA, Naoji , ARITA, Hisashi , ISHIKAWA, Kenji , NINOMIYA, Yuichi , OTSUKA, Yoshimichi , KAWASHIMA, Tadashi , IWAMOTO, Takushi
发明人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , NIPPON HOSO KYOKAI
IPC分类号： H04B14/06
CPC分类号： H04N7/088 , H04B14/046
摘要： A circuit for demodulating digital voice signals to suppress the broken noise that generates when the synchronism is no more maintained or when the mute is forcibly applied. The demodulation circuit comprises a synchronism detecting circuit (18) and a muting circuit (17) which mutes the output of an interpolation circuit (16) responsive to a synchronizing lock signal produced from the synchronism detecting circuit (18) when the synchronism is no more maintained. The output of the interpolation circuit (16) that is a differential signal is muted and is then integrated to produce a voice signal of high sound quality without noise even when synchronism is not maintained.
摘要翻译：用于解调数字语音信号以抑制当不再保持同步或当静音被强制应用时产生的破坏的噪声的电路。解调电路包括同步检测电路（18）和静噪电路（17），该静噪电路（17）响应于同步不再多于同步检测电路（18）产生的同步锁定信号，使内插电路（16）的输出静音保持。作为差分信号的内插电路（16）的输出被静音，然后被积分，即使在不保持同步的情况下也产生没有噪声的高音质的语音信号。

40. 发明申请

WO1988010035A1 PROTECTION OF ENERGY INFORMATION IN SUB-BAND CODING 审中-公开
标题翻译：保护子带编码中的能源信息
公开(公告)号：WO1988010035A1
公开(公告)日：1988-12-15
申请号：PCT/US1988001790
申请日：1988-05-31
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , MCLAUGHLIN, Michael, Joseph , RASKY, Phillip, D.
IPC分类号： H04B14/06
CPC分类号： H04L1/007 , G10L19/005 , H03M13/35 , H04B1/667
摘要： An encoding system for transmission and reception of speech signals and utilizing sampling, filtering (12) and sub-band coding (14) techniques for reduction of the bit rate. The energy levels of each sub-band are determined with respect to the band having the maximum energy level. The energy level information is encoded and divided into protected and unprotected bits. Only the protected bits are used for the determination of the bit allocation of the sample information, but both protected and unprotected bits are utilized in reconstituting the original levels of the bands.
摘要翻译：一种用于发送和接收语音信号的编码系统，并利用采样，滤波（12）和子带编码（14）技术来降低比特率。相对于具有最大能级的频带确定每个子带的能级。能级信息被编码并分为受保护和不受保护的位。只有受保护的比特被用于确定样本信息的比特分配，但是利用保护的和不受保护的比特来重构波段的原始级别。

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