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    • 38. 发明申请
    • ALTERNATE TIMING SIGNAL FOR A VESTIGIAL SIDEBAND MODULATOR
    • VESTIGIAL侧边调制器的替代时序信号
    • WO2003047089A1
    • 2003-06-05
    • PCT/US2002/037959
    • 2002-11-25
    • THOMSON LICENSING S.A.KNUTSON, Paul, Gothard
    • KNUTSON, Paul, Gothard
    • H03C1/52
    • H04N21/426H04B1/68H04N5/4401
    • A remodulator timing signal (35) is generated by a phase locked loop (33) which is coupled to a broadcast vestigial sideband signal (5). Within the signal (5) is highly accurate timing data which is coupled to a demodulator (31). Timing signals to the demodulator are provided by a variable frequency oscillator (32) which receives a correction signal from a phase locked loop (33) housed within the demodulator. The phase locked loop generates the correction signal by comparing the VFO output frequency (36) with the timing data embedded within the broadcast signal (5). A value register (203,303,403) maintains the recent average VFO frequency. A multiplexer (204,304,404) selects the value register data to control the VFO (32,220,320) in the absence of the broadcast timing data.
    • 通过耦合到广播残留边带信号(5)的锁相环(33)产生再调制定时信号(35)。 信号(5)内的高精度时序数据被耦合到解调器(31)。 解调器的定时信号由可变频率振荡器(32)提供,该可变频率振荡器从容纳在解调器内的锁相环(33)接收校正信号。 锁相环通过将VFO输出频率(36)与嵌入在广播信号(5)内的定时数据进行比较来产生校正信号。 值寄存器(203,303,403)保持最近的平均VFO频率。 在没有广播定时数据的情况下,多路复用器(204,304,404)选择值寄存器数据来控制VFO(32,220,320)。