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31. 发明申请

WO2006055191A3 FUNCTIONAL PARTITIONING METHOD FOR PROVIDING MODULAR DATA STORAGE SYSTEMS 审中-公开
公开(公告)号：WO2006055191A3
公开(公告)日：2006-05-26
申请号：PCT/US2005/038473
申请日：2005-10-24
申请人： SUN MICROSYSTEMS, INC. , CHAWLA, Gaurav , DEKONING, Rodney , CLARKE, Kevin, J.
发明人： CHAWLA, Gaurav , DEKONING, Rodney , CLARKE, Kevin, J.
IPC分类号： G06F12/00 , G06F13/00
摘要： A modular data storage system (110) with a control path and a data path. The storage system (110) includes three modular components linked and adapted for independent removal and insertion within the modular data storage system (110). A service processor (114) is positioned in the control path, a data services platform (120) is positioned in the data path and the control path, and a storage array controller (130) is positioned in the data path and the control path. The data services platform (120) has a host interface (122) interfacing with storage application hosts (150) and includes a control path block (124) linked to the service processor (114). The platform (120) includes a data path block (128) including data path functions that may be functions partitioned for performance only by the data services platform (120). The storage array controller (130) includes a control path block (132) linked to the service processor and including control interfaces. The controller (130) includes a data path block (134) including data path functions.

32. 发明申请

WO2006055191A2 FUNCTIONAL PARTITIONING METHOD FOR PROVIDING MODULAR DATA STORAGE SYSTEMS 审中-公开
标题翻译：提供模块化数据存储系统的功能分区方法
公开(公告)号：WO2006055191A2
公开(公告)日：2006-05-26
申请号：PCT/US2005038473
申请日：2005-10-24
申请人： SUN MICROSYSTEMS INC , CHAWLA GAURAV , DEKONING RODNEY , CLARKE KEVIN J
发明人： CHAWLA GAURAV , DEKONING RODNEY , CLARKE KEVIN J
IPC分类号： G06F12/16
CPC分类号： G06F3/0658 , G06F3/0607 , G06F3/0683 , G06F11/1076 , G06F11/1092 , G06F11/2294
摘要： A modular data storage system with a control path and a data path. The storage system includes three modular components linked and adapted for independent removal and insertion within the modular data storage system. A service processor is positioned in the control path, a data services platform is positioned in the data path and the control path, and a storage array controller is positioned in the data path and the control path. The data services platform has a host interface interfacing with storage application hosts and includes a control path block linked to the service processor. The platform includes a data path block including data path functions that may be functions partitioned for performance only by the data services platform. The storage array controller includes a control path block linked to the service processor and including control interfaces. The controller includes a data path block including data path functions.
摘要翻译：具有控制路径和数据路径的模块化数据存储系统。存储系统包括三个模块化组件，链接并适用于模块化数据存储系统内的独立拆卸和插入。服务处理器位于控制路径中，数据服务平台位于数据路径和控制路径中，并且存储阵列控制器位于数据路径和控制路径中。数据服务平台具有与存储应用主机接口的主机接口，并且包括链接到服务处理器的控制路径块。该平台包括数据路径块，其包括数据路径功能，其可以是分区的功能，仅由数据服务平台执行。存储阵列控制器包括链接到服务处理器并包括控制接口的控制路径块。控制器包括包括数据路径功能的数据路径块。

33. 发明申请

WO2005020067A3 MULTI-CORE MULTI-THREAD PROCESSOR 审中-公开
标题翻译：多核多线程处理器
公开(公告)号：WO2005020067A3
公开(公告)日：2006-05-26
申请号：PCT/US2004024956
申请日：2004-07-30
申请人： SUN MICROSYSTEMS INC , OLUKOTUN KUNLE A
发明人： OLUKOTUN KUNLE A
IPC分类号： G06F9/38 , G06F9/30 , G06F9/315 , G06F12/08 , G06F15/78
CPC分类号： G06F9/3834 , G06F9/30032 , G06F9/30047 , G06F9/30087 , G06F9/3009 , G06F9/30141 , G06F9/3828 , G06F9/3851 , G06F9/3861 , G06F9/3891 , G06F12/0811 , G06F12/0813 , G06F12/0842 , G06F15/167 , G06F15/781
摘要： A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.
摘要翻译：提供处理器。处理器包括至少两个核。至少两个内核具有第一级缓存，并且是多线程的。包括交叉开关。提供了通过横杆与至少两个核心通信的多个高速缓存组存储器。多个高速缓存组存储器中的每一个与主存储器接口通信。包括与主存储器接口通信并提供到至少两个核的链接的多个输入/输出接口模块。链路绕过多个高速缓存组存储器和交叉开关。被配置为使得至少两个核能够以隐藏由高速缓存访问引起的延迟的方式从第一线程切换到第二线程的线程硬件被包括。包括用于确定何时切换多核多线程环境中的线程的服务器和方法。

34. 发明申请

WO2005124860A3 MEMORY MODULE COOLING 审中-公开
标题翻译：内存模块冷却
公开(公告)号：WO2005124860A3
公开(公告)日：2006-04-27
申请号：PCT/US2005019964
申请日：2005-06-07
申请人： SUN MICROSYSTEMS INC , GATES WILLIAM GEORGE , HARRIS RICHARD JOHN , WRYCRAFT SEAN CONOR
发明人： GATES WILLIAM GEORGE , HARRIS RICHARD JOHN , WRYCRAFT SEAN CONOR
IPC分类号： H01L23/367
CPC分类号： H01L23/3672 , H01L2924/0002 , H01L2924/00
摘要： A heatsink for a memory module includes a substantially planar contact portion for forming a thermal contact with the memory module and for mounting the heatsink on the memory module. One or more formations for emitting heat are also provided, the formations for emitting heat being in thermal communication with the contact portions.
摘要翻译：用于存储器模块的散热器包括用于形成与存储器模块的热接触并用于将散热器安装在存储器模块上的基本上平面的接触部分。还提供了一个或多个用于发热的结构，用于发射热量的结构与接触部分热连通。

35. 发明申请

WO2006007075A2 SELECTIVELY PERFORMING FETCHES FOR STORE OPERATIONS DURING SPECULATIVE EXECUTION 审中-公开
标题翻译：选择性地执行储存运营期间的投注
公开(公告)号：WO2006007075A2
公开(公告)日：2006-01-19
申请号：PCT/US2005/016434
申请日：2005-05-11
申请人： SUN MICROSYSTEMS, INC. , CHAUDHRY, Shailender , TREMBLAY, Marc , CAPRIOLI, Paul
发明人： CHAUDHRY, Shailender , TREMBLAY, Marc , CAPRIOLI, Paul
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3834 , G06F12/0862
摘要： One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.
摘要翻译：本发明的一个实施例提供了一种处理器，其在推测执行期间选择性地提取用于存储指令的高速缓存行。在正常执行期间，处理器按程序顺序发出执行指令。在遇到产生启动条件的指令时，处理器执行检查点并开始以推测执行模式执行指令。在推测执行模式期间遇到存储指令时，处理器检查L1数据高速缓存以寻找匹配的高速缓存行，并检查存储的存储缓冲区以匹配高速缓存行。如果匹配高速缓存行已经存在于L1数据高速缓存中，或者如果到匹配高速缓存行的存储已存在于存储缓冲区中，则处理器会抑制生成高速缓存行的提取。否则，处理器会为缓存行生成一个提取。

36. 发明申请

WO2006005025A2 THREAD-BASED CLOCK ENABLING IN A MULTI-THREADED PROCESSOR 审中-公开
标题翻译：基于螺纹的时钟在多线程处理器中启用
公开(公告)号：WO2006005025A2
公开(公告)日：2006-01-12
申请号：PCT/US2005/023647
申请日：2005-06-30
申请人： SUN MICROSYSTEMS, INC. , GOLLA, Robert, T. , BROOKS, Jeffrey, S. , OLSON, Christopher, H.
发明人： GOLLA, Robert, T. , BROOKS, Jeffrey, S. , OLSON, Christopher, H.
IPC分类号： G06F9/38
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G06F9/3851 , Y02D10/128 , Y02D10/171
摘要： A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.
摘要翻译：一种用于控制多线程处理器中的功耗的方法和装置。在一个实施例中，处理器包括用于处理指令的至少一个逻辑单元。逻辑单元包括多个位置，其中多个位置中的每一个对应于至少一个指令线程。时钟信号可以经由时钟门控单元提供给逻辑单元。时钟门控单元被配置为当没有指令线程对于该位置有效时，禁止将时钟信号提供给相应的一个线程位置。禁止线程位置的时钟信号可能会降低处理器的功耗。

37. 发明申请

WO2006004826A3 APPARATUS AND METHOD FOR FINE-GRAINED MULTITHREADING IN A MULTIPIPELINED PROCESSOR CORE 审中-公开
公开(公告)号：WO2006004826A3
公开(公告)日：2006-01-12
申请号：PCT/US2005/023077
申请日：2005-06-30
申请人： SUN MICROSYSTEMS, INC. , HETHERINGTON, Ricky, C. , GROHOSKI, Gregory, F. , GOLLA, Robert, T.
发明人： HETHERINGTON, Ricky, C. , GROHOSKI, Gregory, F. , GOLLA, Robert, T.
IPC分类号： G06F9/46 , G06F9/30
摘要： An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, where each of the plurality of thread groups may comprise a subset of the plurality of threads, to issue a first instruction from one of the plurality of threads during one execution cycle, and to issue a second instruction from another one of the plurality of threads during a successive execution cycle. The processor may further include a plurality of execution units, each configured to execute instructions issued from a respective thread group.

38. 发明申请

WO2006004826A2 APPARATUS AND METHOD FOR FINE-GRAINED MULTITHREADING IN A MULTIPIPELINED PROCESSOR CORE 审中-公开
标题翻译：用于多管线处理器核心中的细粒度多线程处理的装置和方法
公开(公告)号：WO2006004826A2
公开(公告)日：2006-01-12
申请号：PCT/US2005023077
申请日：2005-06-30
申请人： SUN MICROSYSTEMS INC , HETHERINGTON RICKY C , GROHOSKI GREGORY F , GOLLA ROBERT T
发明人： HETHERINGTON RICKY C , GROHOSKI GREGORY F , GOLLA ROBERT T
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3885 , G06F12/0842 , G06F12/0859
摘要： An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, where each of the plurality of thread groups may comprise a subset of the plurality of threads, to issue a first instruction from one of the plurality of threads during one execution cycle, and to issue a second instruction from another one of the plurality of threads during a successive execution cycle. The processor may further include a plurality of execution units, each configured to execute instructions issued from a respective thread group.
摘要翻译：用于多分支处理器核心中的细粒度多线程的设备和方法。根据一个实施例，处理器可以包括指令提取逻辑，其被配置为将多个线程中给定的一个线程分配给多个线程组中的相应一个线程组，其中多个线程组中的每一个可以包括多个线程组中的子集线程在一个执行周期期间从多个线程中的一个线程发出第一指令，并且在连续执行周期期间从多个线程中的另一个发出第二指令。处理器还可以包括多个执行单元，每个执行单元被配置为执行从相应线程组发出的指令。

39. 发明申请

WO2006001946A2 MECHANISM FOR ELIMINATING THE RESTART PENALTY WHEN REISSUING DEFERRED INSTRUCTIONS 审中-公开
标题翻译：在发布指令时消除重新起诉的机制
公开(公告)号：WO2006001946A2
公开(公告)日：2006-01-05
申请号：PCT/US2005/017454
申请日：2005-05-18
申请人： SUN MICROSYSTEMS, INC. , CHAUDRY, Shailender , CAPRIOLI, Paul , TREMBLAY, Marc
发明人： CHAUDRY, Shailender , CAPRIOLI, Paul , TREMBLAY, Marc
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3863
摘要： One embodiment of the present invention provides a system which facilitates eliminating a restart penalty when reissuing deferred instructions in a processor that supports speculative-execution. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. When an unresolved data dependency is resolved during execute-ahead mode, the processor begins to execute the deferred instructions in a deferred mode. In doing so, the processor initially issues deferred instructions, which have already been decoded, from a deferred queue. Simultaneously, the processor feeds instructions from a deferred SRAM into the decode unit, and these instructions eventually pass into the deferred queue.
摘要翻译：本发明的一个实施例提供了一种在支持推测执行的处理器中重新发布延迟指令时有助于消除重新启动损失的系统。在正常执行模式下，系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖关系时，处理器执行检查点操作并以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟，并且其中其他非延迟指令以程序顺序执行。当在执行提前模式下解决未解决的数据依赖关系时，处理器开始以延迟模式执行延迟指令。在这样做时，处理器最初从延迟队列中发出已被解码的延迟指令。同时，处理器将来自延迟SRAM的指令送入解码单元，并且这些指令最终进入延迟队列。

40. 发明申请

WO2005121949A2 AVOIDING REGISTER RAW HAZARDS WHEN RETURNING FROM SPECULATIVE EXECUTION 审中-公开
标题翻译：当从行政执行返回时避免注册原始危险
公开(公告)号：WO2005121949A2
公开(公告)日：2005-12-22
申请号：PCT/US2005006185
申请日：2005-02-25
申请人： SUN MICROSYSTEMS INC , CHAUDHRY SHAILDENDER , CAPRIOLI PAUL , YIP SHERMAN H
发明人： CHAUDHRY SHAILDENDER , CAPRIOLI PAUL , YIP SHERMAN H
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During operation, the system issues instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commences execution in the speculative-execution mode. Upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the system uses the checkpoint to resume execution in the normal-execution mode from the launch-point instruction. In doing so, the system ensures that entries. that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for in order to prevent register RAW hazard when resuming execution from the launch-point instruction.
摘要翻译：本发明的一个实施例提供一种从推测执行模式返回时避免寄存器读写（RAW）危险的系统。该系统在具有按顺序架构的处理器内工作，其中处理器包括短延迟记分板，其延迟取决于未完成的短延迟指令的指令的发布。在操作期间，系统在以正常执行模式执行程序期间以程序顺序发出执行指令。在导致处理器进入推测执行模式的指令（发起点指令）期间遇到条件（启动条件）时，系统生成检查点，该检查点随后可用于将程序的执行返回到启动点指令，并以推测执行模式开始执行。当遇到导致处理器离开推测执行模式并返回到启动点指令的条件时，系统使用检查点在正常执行模式下从启动点指令恢复执行。在这样做时，系统确保输入。在进入推测执行模式之前处于短暂延迟记分板中，并且尚未解决的情况被考虑，以便在从启动点指令恢复执行时防止寄存器RAW危险。

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