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21. 发明申请

WO2019001926A1 PRE-DRIVER 审中-公开
公开(公告)号：WO2019001926A1
公开(公告)日：2019-01-03
申请号：PCT/EP2018/065068
申请日：2018-06-07
申请人： ROBERT BOSCH GMBH
发明人： DING, Qibing , JIANG, Ming
IPC分类号： H03K17/687 , H03K19/003 , H03K17/0812
摘要： The present invention relates to a pre-driver, comprising: a first field effect transistor (Mpu), with a source thereof being connected to a power supply input pin (VPR) of the pre-driver; a second field effect transistor (Mpd), with a drain thereof being connected to a drain of the first field effect transistor and connected to a first output pin (Gate) of the pre-driver, and a source of the second field effect transistor being connected to a second output pin (Srce) of the pre-driver, wherein the first and second field effect transistors are controlled to switch on alternately; a third field effect transistor (Mshort), with a source thereof being connected to ground; a reverse protection circuit (Mreverse), for preventing current flow from the ground to the second output pin; and a first control circuit (20), for causing the third field effect transistor to be in an OFF state when a control signal (Cfg_LS) indicates that the pre-driver is used as a high-side driver or when the control signal indicates that the pre-driver is used as a low-side driver and a voltage of the first output pin is greater than a voltage threshold, and for causing the third field effect transistor to be in an ON state when the control signal indicates that the pre-driver is used as a low-side driver and a voltage of the first output pin is not greater than the voltage threshold. The pre-driver can bear a greater voltage.

22. 发明申请

WO2018231148A1 CIRCUIT AND METHOD OF FORMING THE SAME 审中-公开
公开(公告)号：WO2018231148A1
公开(公告)日：2018-12-20
申请号：PCT/SG2018/050265
申请日：2018-05-30
申请人： NANYANG TECHNOLOGICAL UNIVERSITY
发明人： CHANG, Joseph Sylvester , CHONG, Kwen Siong , LIN, Tong , LWIN, Ne Kyaw Zwa , HARIHARAKRISHNAN, Sivaramakrishnan
IPC分类号： H03K19/003 , H01L23/552 , H01L27/06 , H03K19/094 , H01L29/78
摘要： According to embodiments of the present invention, a circuit is provided. The circuit includes forming a first electrical device having a first region of a first conductivity type, forming a second electrical device having a second region of a second conductivity type, and electrically coupling the first region and the second region to each other, wherein one of the first and second regions is arranged to at least substantially surround the other of the first and second regions. According to further embodiments of the present invention, a method of forming a circuit is also provided.

23. 发明申请

WO2018175097A1 APPARATUS AND METHOD FOR LATCHING DATA INCLUDING AND-NOR OR OR-NAND GATE AND FEEDBACK PATHS 审中-公开
公开(公告)号：WO2018175097A1
公开(公告)日：2018-09-27
申请号：PCT/US2018/020881
申请日：2018-03-05
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Changho , YANG, Derek , YOON, Sei Seung
IPC分类号： H03K3/012 , H03K3/037 , H03K19/0948 , H03K19/20 , H03K19/003
摘要： A latch circuit (200) includes an AND-NOR gate (210), a NAND gate (230), and a NOR gate (220). The AND-NOR gate includes a first AND-input configured to receive input data (DIN) and a second AND- input coupled to an output (A) of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output (B) of the NOR gate, and an output configured to generate output data (Dout). The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal (CLK). The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal (CLK/). During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

24. 发明申请

WO2018047124A1 METHOD AND CIRCUIT STRUCTURE FOR SUPPRESSING SINGLE EVENT TRANSIENTS OR GLITCHES IN DIGITAL ELECTRONIC CIRCUITS 审中-公开
标题翻译：用于抑制数字电子电路中的单事件瞬态或击穿的方法和电路结构
公开(公告)号：WO2018047124A1
公开(公告)日：2018-03-15
申请号：PCT/IB2017/055455
申请日：2017-09-11
申请人： NELSON MANDELA UNIVERSITY
发明人： SMITH, Farouk
IPC分类号： H03K19/003 , H03K19/007
摘要： A circuit structure and a method for supressing single event transients (SETs) or glitches in digital electronic circuits are provided. The circuit includes a first input which receives an output of a digital electronic circuit and a second input which receives a redundant or duplicated output of the digital electronic circuit. The circuit includes only four two-input gates of two different kinds selected from AND, OR, NAND and NOR gates. The four two-input gates being arranged so that a final circuit output is impervious to a change in a logic level of only the first input or only the second input, and the final circuit output is equivalent to the logic level of the first and second inputs when the logic level of the first and second inputs match.
摘要翻译：提供了用于抑制数字电子电路中的单个事件瞬变（SET）或毛刺的电路结构和方法。该电路包括接收数字电子电路的输出的第一输入和接收数字电子电路的冗余或重复输出的第二输入。该电路仅包括四个选择从AND，OR，NAND和NOR门的两种不同类型的双输入门。四个双输入门被布置为使得最终电路输出不受仅第一输入或仅第二输入的逻辑电平的变化影响，并且最终电路输出等同于第一和第二输入的逻辑电平当第一和第二输入的逻辑电平匹配时输入。

25. 发明申请

WO2018034769A1 VOTING CIRCUIT AND SELF-CORRECTING LATCHES 审中-公开
标题翻译：表决电路和自我修正的锁存器
公开(公告)号：WO2018034769A1
公开(公告)日：2018-02-22
申请号：PCT/US2017/042549
申请日：2017-07-18
申请人： XILINX, INC.
发明人： NGUYEN, Chi, M. , FU, Robert, I.
IPC分类号： H03K19/003 , H03K19/23
摘要： The disclosed voting circuit includes a pull-up circuit (110) connected to an output node (126) and to a positive supply voltage (122). A pull-down circuit (112) is connected to the output node (126) and to ground (124), and the output node (126) is coupled to receive true output of a first bi-stable circuit (104). The pull-up circuit (1 10) pulls the output node (126) to the positive supply voltage in response to complementary output signals from second (106) and third (108) bistable circuits being in a first state, and the pull-down circuit (1 12) pulls the output node (126) to ground (124) in response to complementary output signals from second (106) and third (108) bi-stable circuits being in a second state that is opposite the first state.
摘要翻译：所公开的投票电路包括连接到输出节点（126）和正电源电压（122）的上拉电路（110）。下拉电路（112）连接到输出节点（126）和接地（124），并且输出节点（126）被耦合以接收第一双稳态电路（104）的真实输出。响应于来自第二（106）和第三（108）双稳电路的互补输出信号处于第一状态，上拉电路（110）将输出节点（126）拉至正电源电压，并且下拉响应于来自第二（106）和第三（108）双稳电路的互补输出信号处于与第一状态相反的第二状态，电路（112）将输出节点（126）拉到地（124） / p>

26. 发明申请

WO2017172002A1 ELECTROSTATIC DISCHARGE (ESD) ISOLATED INPUT/OUTPUT (I/O) CIRCUITS 审中-公开
标题翻译：静电放电（ESD）隔离输入/输出（I / O）电路
公开(公告)号：WO2017172002A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/014949
申请日：2017-01-25
申请人： QUALCOMM INCORPORATED
发明人： WORLEY, Eugene Robert , JALILIZEINALI, Reza , DUNDIGAL, Sreeker , CHEN, Wen-Yi , CHILLARA, Krishna Chaitanya , KANG, Taeghyun
IPC分类号： H03K19/003 , H03K19/0185
摘要： A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal (102) from a pair of I/O transistors of the SERDES differential I/O circuit (120) in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal (104) from the pair of I/O transistors of the SERDES differential I/O circuit (120) in response to the detected electrostatic discharge event.
摘要翻译：保护串行器/解串器（SERDES）差分输入/输出（I / O）电路的方法包括检测静电放电事件。该方法还包括响应于检测到的静电放电事件，选择性地使电源端子（102）与SERDES差分I / O电路（120）的一对I / O晶体管分离。该方法还包括响应于检测到的静电放电事件选择性地将接地端子（104）与SERDES差分I / O电路（120）的一对I / O晶体管分离。

27. 发明申请

WO2017057046A1 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：WO2017057046A1
公开(公告)日：2017-04-06
申请号：PCT/JP2016/077402
申请日：2016-09-16
申请人：ソニー株式会社
发明人：神田　泰夫 , 横山　孝司
IPC分类号： H03K19/003 , H01L21/82 , H01L21/822 , H01L21/8244 , H01L21/8246 , H01L27/04 , H01L27/105 , H01L27/11 , H01L29/82 , H01L43/08 , H01L45/00 , H01L49/00 , H03K19/0948 , H03K19/177
CPC分类号： H01L21/82 , H01L21/822 , H01L27/04 , H01L27/105 , H01L27/11 , H01L29/82 , H01L43/08 , H01L45/00 , H01L49/00 , H03K19/003 , H03K19/0948 , H03K19/177
摘要：本技術は、歩留まりを向上させることができるようにする半導体装置に関する。揮発性論理回路は、記憶ノードを有しており、入力された情報を記憶する。揮発性論理回路の記憶ノードには、同一の接続ゲートを介して複数の不揮発性素子が接続されており、それらの複数の不揮発性素子のそれぞれには、不揮発性素子ごとに、それらの不揮発性素子を制御するための制御線が接続されている。このように揮発性論理回路に同一の接続ゲートを介して複数の不揮発性素子を接続することで、歩留まりを向上させることができる。本技術は半導体装置に適用することができる。
摘要翻译：本发明涉及能够提高产量的半导体装置。本发明的易失性逻辑电路具有存储节点，并存储输入的信息。多个非易失性元件通过相同的连接门连接到易失性逻辑电路的存储节点，用于控制非易失性元件的控制线分别连接到非易失性元件。以这种方式，非易失性元件通过相同的连接栅极连接到易失性逻辑电路，从而提高产量。现有技术可以应用于半导体器件。

28. 发明申请

WO2017007559A1 INPUT/OUTPUT (I/O) DRIVER 审中-公开
标题翻译：输入/输出（I / O）驱动器
公开(公告)号：WO2017007559A1
公开(公告)日：2017-01-12
申请号：PCT/US2016/036075
申请日：2016-06-06
申请人： QUALCOMM INCORPORATED
发明人： AZIN, Meysam
IPC分类号： H03K19/003
CPC分类号： H03K5/04 , H03K19/0016 , H03K19/00361 , H03K19/018507
摘要： An I/O driver (200) and related method are provided herein. The I/O driver (200) includes circuitry for expediting the configuring of the corresponding output FET (pull-up P1, Pull-down N1) to operate in the linear region to reduce delay between the transition of the input signal (D0) and the corresponding transition of the output signal (V0). Additionally, the I/O driver (200) includes circuitry (220, 210, IP, IN, Cfp, Cfn) for controlling the slew rate at which the output signal transitions (Common node P1, N1, V0) from a low logic state to a high logic state, or vice-versa. Further, the I/O driver includes circuitry (210, 220, IP, IN, Cfp, Cfn) for turning off the turned-on output FET (P1 as example) before turning on the other output FET (N1 as example). This prevents "shoot-thru" current from flowing through the output FETs (P1, N1) to reduce power consumption associated with the I/O driver (200).
摘要翻译：本文提供了一种I / O驱动程序（200）及相关方法。 I / O驱动器（200）包括用于加速配置相应的输出FET（上拉P1，下拉N1）以在线性区域中操作的电路，以减少输入信号（D0）和输出信号（V0）的相应转换。此外，I / O驱动器（200）包括用于控制输出信号从低逻辑状态转换（公共节点P1，N1，V0）的转换速率的电路（220,210，IP，IN，Cfp，Cfn）到高逻辑状态，反之亦然。此外，I / O驱动器包括用于在接通另一输出FET（N1作为示例）之前关断导通输出FET（例如，P1）的电路（210,220，IP，IN，Cfp，Cfn）。这防止“直通”电流流过输出FET（P1，N1），以减少与I / O驱动器（200）相关联的功耗。

29. 发明申请

WO2016185745A1 複合型半導体装置审中-公开
标题翻译：复合半导体器件
公开(公告)号：WO2016185745A1
公开(公告)日：2016-11-24
申请号：PCT/JP2016/055085
申请日：2016-02-22
申请人：シャープ株式会社
发明人：仲嶋　明生 , 一條　尚生
IPC分类号： H01L21/822 , H01L27/04 , H02M7/48 , H03K19/003
CPC分类号： H03K17/082 , H01L21/822 , H01L23/3114 , H01L23/49503 , H01L23/49562 , H01L23/49575 , H01L24/40 , H01L27/04 , H01L2224/40137 , H01L2224/40245 , H01L2924/00014 , H01L2924/10253 , H01L2924/1033 , H01L2924/13062 , H01L2924/13064 , H02M7/003 , H03K17/0828 , H03K17/107 , H03K17/567 , H03K19/003 , H03K2017/6875 , H01L2224/37099
摘要：低オン抵抗であって、かつ負荷短絡時の耐性の高い複合型半導体装置を提供する。互いにカスコード接続されたノーマリオン型の第１ＦＥＴ（Ｑ１）及びノーマリオフ型の第２ＦＥＴ（Ｑ２）を備えている複合型半導体装置（１０）において、第１ＦＥＴ（Ｑ１）のドレインに印加されている電圧が４００Ｖである場合、複合型半導体装置（１０）に接続された負荷の短絡が開始したタイミングからの経過時間を短絡後経過時間Ｔとし、第２ＦＥＴのオン抵抗の値をＲｏｎＱ２、第１ＦＥＴの閾値電圧をＶＴＨＱ１、第１ＦＥＴのゲート電圧が０Ｖのときの、第１ＦＥＴの飽和状態における第１ＦＥＴのドレイン電流をＩｄｍａｘ１とし、短絡後経過時間Ｔ≧２μｓｅｃの間、第１ＦＥＴの破壊を防ぐ程度に制限したドレイン電流をＩｄｍａｘとするときに以下の式の関係を満たす。
摘要翻译：提供了具有低导通电阻并且高耐承载负载短路的复合半导体器件。一种复合半导体器件（10），其具有彼此串联连接的常通的第一FET（Q1）和常关的第二FET（Q2）。当T是从连接到复合半导体器件（10）的负载的短路开始所经过的时间之后的短路后经过时间，RonQ2是第二FET的导通电阻值， VTHQ1是第一FET的阈值电压，Idmax1是第一FET处于中性状态时的第一FET的漏极电流，第一FET的栅极电压为0V，Idmax为限制第一FET的漏极电流当短路后经过时间T大于或等于2微秒时，FET断开，当施加到第一FET（Q1）的漏极的电压为400V时，本发明满足给定的公式。

30. 发明申请

WO2016182676A1 UNCERTAINTY AWARE INTERCONNECT DESIGN TO IMPROVE CIRCUIT PERFORMANCE AND/OR YIELD 审中-公开
标题翻译：不确定性互连设计，以提高电路性能和/或电流
公开(公告)号：WO2016182676A1
公开(公告)日：2016-11-17
申请号：PCT/US2016/027627
申请日：2016-04-14
申请人： QUALCOMM INCORPORATED
发明人： LIU, Chunchen , LAW, Oscar Ming Kin , LU, Ju-Yi , CHEN, Po-Hung , DUAN, Zhengyu
IPC分类号： G01R31/3193 , H03K3/03 , H03K19/003
CPC分类号： H03K3/0315 , G01R31/31937 , G06F17/5045 , G06F17/5068 , G06F17/5081 , H01L27/0207 , H01L27/11807 , H03K3/012 , H03K19/00346
摘要： Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal (410) produced by a first ring oscillator (404) that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit (406, 408) that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit (406, 408), and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal (410) produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal (410) when the second ring oscillator circuit is operated in the second mode.
摘要翻译：描述了与用于制造半导体IC器件的参数和指导相关的方法和装置。一种方法包括测量由第一环形振荡器（404）产生的第一振荡信号（410），所述第一振荡信号包括设置在IC的第一互连层中的第一互连，为第二环形振荡器电路选择第一工作模式（406， 408），其包括与所述第一互连对准布置的第二互连，为所述第二环形振荡器电路（406,408）选择第二工作模式，以及基于所述第一互连的频率差来确定所述第一互连的一个或多个特性当第二环形振荡器电路在第二模式下操作时，当第二环形振荡器电路以第一模式操作时产生的第一振荡信号（410）和第一振荡信号（410）的频率产生。

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