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21. 发明申请

WO2017027074A1 TUNNEL BARRIER SCHOTTKY 审中-公开
公开(公告)号：WO2017027074A1
公开(公告)日：2017-02-16
申请号：PCT/US2016/027750
申请日：2016-04-15
申请人： HRL LABORATORIES, LLC
发明人： CHU, Rongming , CAO, Yu , LI, Zijian , WILLIAMS, Adam, J.
IPC分类号： H01L29/872 , H01L29/47
CPC分类号： H01L29/205 , H01L29/0619 , H01L29/2003 , H01L29/66212 , H01L29/872
摘要： A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AIGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.
摘要翻译：二极管包括：半导体衬底; 接触所述基板的底部的阴极金属层; 衬底上的半导体漂移层; 在漂移层上的梯度级的氮化铝镓（AIGaN）半导体势垒层，并且具有比漂移层更大的带隙，所述阻挡层在漂移层和顶表面之间具有顶表面和底表面，所述势垒层具有从底面到顶面增加铝组成; 以及与阻挡层的顶表面直接接触的阳极金属层。

22. 发明申请

WO2017019472A1 METHOD AND APPARATUS FOR CONTROLLED DOPANT INCORPORATION AND ACTIVATION IN A CHEMICAL VAPOR DEPOSITION SYSTEM 审中-公开
标题翻译：化学气相沉积系统中控制剂掺入和活化的方法与装置
公开(公告)号：WO2017019472A1
公开(公告)日：2017-02-02
申请号：PCT/US2016/043462
申请日：2016-07-22
申请人： VEECO INSTRUMENTS INC.
发明人： ARMOUR, Eric, A. , PAPASOULIOTIS, George , KWON, Daewon
IPC分类号： H01L21/02 , H01L21/205 , H01L21/687
CPC分类号： H01L21/3245 , C23C16/047 , C23C16/301 , C23C16/4584 , C23C16/482 , C23C16/52 , H01L21/0254 , H01L21/0262 , H01L29/20 , H01L29/2003 , H01L29/205 , H01L29/66431 , H01L29/7787 , H01L33/0075 , H01L33/32
摘要： Embodiments include systems and methods for producing semiconductor wafers having reduced quantities of point defects. These systems and methods include a tunable ultraviolet (UV) light source, which is controlled to produce a raster of a UV light beam across a surface of a semiconductor wafer during epitaxial growth to dissociate point defects in the semiconductor wafer. In various embodiments, the tunable UV light source is configured external to a Metal Organic Chemical Vapor Deposition (MOCVD) chamber and controlled such that the UV light beam is directed though a window defined in a wall of the MOCVD chamber.
摘要翻译：实施例包括用于制造具有减少量的点缺陷的半导体晶片的系统和方法。这些系统和方法包括可调紫外（UV）光源，其被控制以在外延生长期间跨越半导体晶片的表面产生UV光束的光栅，以解离半导体晶片中的点缺陷。在各种实施例中，可调谐UV光源被配置在金属有机化学气相沉积（MOCVD）室的外部，并被控制使得UV光束被引导通过限定在MOCVD室的壁中的窗口。

23. 发明申请

WO2017005684A1 JUNCTION BARRIER SCHOTTKY DIODE WITH ENHANCED SURGE CURRENT CAPABILITY 审中-公开
标题翻译：具有增强浪涌电流能力的接线棒肖特基二极管
公开(公告)号：WO2017005684A1
公开(公告)日：2017-01-12
申请号：PCT/EP2016/065681
申请日：2016-07-04
申请人： ABB SCHWEIZ AG
发明人： MIHAILA, Andrei , RAHIMO, Munaf , MINAMISAWA, Renato , KNOLL, Lars , STORASTA, Liutauras
IPC分类号： H01L29/872 , H01L29/06 , H01L29/16 , H01L29/20
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0692 , H01L29/1608 , H01L29/2003
摘要： A semiconductor power rectifier with increased surge current capability is described, which has a semiconductor layer (64) having a first main side (52) and a second main side (53) opposite to the first main side (52). The semiconductor layer (64) includes a drift layer (55) having a first conductivity type, at least one pilot region (65) having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions (56) having the second conductivity type, and a transition region (57) having the second conductivity type, wherein the at least one pilot region (65) has in any lateral direction parallel to the first main side (52) a width of at least 200 µm and is formed adjacent to the first main side (52) to form a first p-n junction with the drift layer (55), each emitter region (56) is formed adjacent to the first main side (52) form a second p-n junction with the drift layer (55), and the transition region (57) is formed adjacent to the first main side (52) to form a third p-n junction with the drift layer (55). The least one pilot region (65) is connected to the transition region (57) by the plurality of stripe-shaped emitter regions (56).
摘要翻译：描述了具有增加的浪涌电流能力的半导体功率整流器，其具有具有与第一主侧（52）相对的第一主侧（52）和第二主侧（53）的半导体层（64）。半导体层（64）包括具有第一导电类型的漂移层（55），具有不同于第一导电类型的第二导电类型的至少一个引导区域（65），多个条形发射极区域（56）具有第二导电类型和具有第二导电类型的过渡区域（57），其中所述至少一个引导区域（65）在与第一主侧（52）平行的任何横向方向上具有至少200μm的宽度并且与第一主侧相邻地形成与漂移层（55）形成的第一pn结，每个发射区（56）形成为与第一主侧（52）相邻，形成与第一主面漂移层（55），并且过渡区域（57）形成为与第一主侧（52）相邻以与漂移层（55）形成第三pn结。所述至少一个导频区域（65）通过所述多个条形发射极区域（56）连接到所述过渡区域（57）。

24. 发明申请

WO2017002793A1 半導体装置および半導体装置の製造方法审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：WO2017002793A1
公开(公告)日：2017-01-05
申请号：PCT/JP2016/069099
申请日：2016-06-28
申请人：三菱電機株式会社
发明人：巽　裕章 , 熊田　翔 , 鈴木　修 , 川端　大輔
IPC分类号： H01L21/52 , H01L21/60 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L24/32 , H01L21/50 , H01L21/52 , H01L23/12 , H01L23/49866 , H01L24/83 , H01L25/07 , H01L25/072 , H01L25/18 , H01L29/1602 , H01L29/1608 , H01L29/20 , H01L29/2003 , H01L29/7393 , H01L29/78 , H01L29/861 , H01L2224/29139 , H01L2224/3207 , H01L2224/83385
摘要：半導体装置（１）は、平坦部と、凹部からなる非平坦部（６）とを有する電極（２２）と、電極（２２）の平坦部および非平坦部（６）上に設けられた金属結晶粒の焼結体からなる接合層（３）と、接合層（３）を介して電極（２２）に接合された半導体素子（４）、（５）と、を備え、接合層（３）は、非平坦部（６）と半導体素子（４）、（５）とに挟まれた第１の領域（３ａ）と、平坦部と半導体素子（４）、（５）とに挟まれた第２の領域（３ｂ）とを有し、第１の領域（３ａ）および第２の領域（３ｂ）のうち層厚が大きい方の領域の金属結晶粒の充填率は、層厚が小さい方の領域の金属結晶粒の充填率より小さい。本発明により、金属結晶粒の焼結体による接合層の信頼性が良好になる。
摘要翻译：该半导体装置（1）设置有：具有平坦部分的电极（22）和包括凹部的非平坦部分（6）由设置在平坦部分上的金属晶体颗粒的烧结体和电极（22）的非平坦部分（6）形成的结合层（3）。以及通过接合层（3）与电极（22）接合的半导体元件（4），（5）。接合层（3）包括夹在非平坦部分（6）和半导体元件（4）或（5）之间的第一区域（3a）和夹在平坦部分和半导体元件之间的第二区域（3b）元素（4）或（5）。在第一区域（3a）和第二区域（3b）之间，具有较大层厚度的区域的金属结晶颗粒的填充率小于层厚度较小的区域的填充率。本发明对由金属结晶颗粒的烧结体形成的接合层提供良好的可靠性。

25. 发明申请

WO2017000906A1 ENHANCEMENT-MODE DOUBLE-CHANNEL HIGH ELECTRON MOBILITY TRANSISTOR 审中-公开
标题翻译：增强型双通道高电子移动晶体管
公开(公告)号：WO2017000906A1
公开(公告)日：2017-01-05
申请号：PCT/CN2016/088062
申请日：2016-07-01
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： CHEN, Jing , WEI, Jin
IPC分类号： H01L29/778
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/517 , H01L29/66204 , H01L29/66462 , H01L29/7783 , H01L29/861
摘要： Enhancement-mode (E-mode) double-channel (DC) HEMTs are provided. In one embodiment a semiconductor device is provided that includes a substrate and a heterostructure formed on the substrate. The heterostructure can include a lower channel layer, an upper channel layer, an insertion layer formed between the lower channel layer and the upper channel layer, and one or more barrier layers formed on the upper channel layer. The semiconductor device further includes a recess formed within the one or more barrier layers and at least a first portion of the upper channel layer, a gate structure formed within the recess. In various implementations, the gate structure has a gate dielectric layer formed on and adjacent to a wall of the recess and a gate electrode formed on and adjacent to the electrode dielectric layer.
摘要翻译：提供增强型（E模式）双通道（DC）HEMT。在一个实施例中，提供了一种半导体器件，其包括衬底和形成在衬底上的异质结构。异质结构可以包括下沟道层，上沟道层，形成在下沟道层和上沟道层之间的插入层以及形成在上沟道层上的一个或多个势垒层。所述半导体器件还包括形成在所述一个或多个阻挡层内的凹部和所述上部沟道层的至少第一部分，形成在所述凹部内的栅极结构。在各种实施方案中，栅极结构具有形成在凹部的壁上并与其相邻的栅极电介质层和形成在电极介电层上并与电极介电层相邻的栅电极。

26. 发明申请

WO2016210449A1 MUTILAYER STRUCTURE CONTAINING A CRYSTAL MATCHING LAYER FOR INCREASED SEMICONDUCTOR DEVICE PERFORMANCE 审中-公开
标题翻译：包含晶体匹配层的多层结构增加了半导体器件性能
公开(公告)号：WO2016210449A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/039675
申请日：2016-06-27
申请人： TIVRA CORPORATION
发明人： MACHUCA, Francisco , WEISS, Robert
IPC分类号： H01L29/20
CPC分类号： H01L33/32 , H01L21/02609 , H01L23/36 , H01L29/04 , H01L29/1075 , H01L29/2003 , H01L29/41758 , H01L29/42316 , H01L29/7786 , H01L29/7788 , H01L29/7789 , H01L33/0075 , H01L33/12 , H01L33/405 , H01L33/64 , H01L2933/0016 , H01L2933/0075
摘要： A multilayer structure comprising a crystal matching layer deposited on a substrate. The crystal matching layer is capable of being used as an ohmic contact, thermal heat sink, and reflective layer. The unique properties of the crystal matching layer allows for the reduction of size of semiconductor devices, a reduction in the fabrication time of semiconductor devices, high current capabilities, high voltage standoff capabilities, and other advantages.
摘要翻译：一种包含沉积在基底上的晶体匹配层的多层结构。晶体匹配层能够用作欧姆接触，热散热器和反射层。晶体匹配层的独特性质允许减小半导体器件的尺寸，减少半导体器件的制造时间，高电流能力，高电压隔离能力以及其他优点。

27. 发明申请

WO2016209282A1 GAN DEVICES ON ENGINEERED SILICON SUBSTRATES 审中-公开
标题翻译：工程硅基板上的GAN器件
公开(公告)号：WO2016209282A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/038095
申请日：2015-06-26
申请人： INTEL CORPORATION
发明人： DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko , TOLCHINSKY, Peter, G. , CHAU, Robert, S.
IPC分类号： H01L29/778 , H01L29/78 , H01L21/336
CPC分类号： H01L25/0657 , H01L21/02381 , H01L21/02428 , H01L21/02458 , H01L21/0254 , H01L21/02658 , H01L21/823871 , H01L21/8252 , H01L21/8258 , H01L23/481 , H01L25/50 , H01L27/0605 , H01L27/0688 , H01L27/085 , H01L27/092 , H01L29/2003 , H01L29/7787 , H01L2225/0652 , H01L2225/06541 , H01L2225/06589
摘要： GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon substrate. A back-side of a silicon substrate may be processed to adapt substrates of standardized diameters and thicknesses to GOS applications. Bowing and/or warping during high temperature epitaxial growth processes may be mitigated by pre-processing silicon substrate so as to pre-stress the substrate in a manner than counterbalances stress induced by the III-N material and/or improve a substrate's ability to absorb stress. III-N devices fabricated on an engineered GOS substrate may be integrated together with silicon MOS devices fabricated on a separate substrate. Structures employed to improve substrate resilience and/or counterbalance the substrate stress induced by the III-N material may be further employed for interconnecting the III-N and silicon MOS devices of a 3D IC.
摘要翻译： GaN-On-Silicon（GOS）结构和用于容纳和/或控制在大直径硅衬底上的III-N生长期间引起的应力/应变的技术。可以处理硅衬底的背面，以将标准化直径和厚度的衬底适应于GOS应用。在高温外延生长过程中的弯曲和/或翘曲可以通过预处理硅衬底来减轻，以便以比由III-N材料诱发的抗衡平衡应力和/或改善衬底吸收能力的方式对衬底预应力强调。在工程GOS衬底上制造的III-N器件可以与在单独衬底上制造的硅MOS器件集成在一起。用于提高衬底弹性和/或平衡由III-N材料引起的衬底应力的结构可进一步用于互连3D IC的III-N和硅MOS器件。

28. 发明申请

WO2016209263A1 GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE 审中-公开
标题翻译：衬底上的氮化镓（GaN）晶体管结构
公开(公告)号：WO2016209263A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/037987
申请日：2015-06-26
申请人： INTEL CORPORATION
发明人： THEN, Han Wui , DASGUPTA, Sansaptak , GARDNER, Sanaz K. , RADOSAVLJEVIC, Marko , SUNG, Seung Hoon , CHAU, Robert S.
IPC分类号： H01L29/778 , H01L29/78
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/775 , H01L29/7783 , H01L29/78 , H01L29/785
摘要： Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.
摘要翻译：公开了氮化镓（GaN）氧化物隔离和在衬底上形成GaN晶体管结构的技术。在某些情况下，GaN晶体管结构可用于体积硅衬底上的高压GaN前端射频（RF）开关的片上系统集成。该技术可以包括例如在衬底中形成多个翅片，将GaN层沉积在翅片上，在GaN层之下的间隙中氧化每个鳍片的至少一部分，以及在GaN层上形成一个或多个晶体管 GaN层。在一些情况下，GaN层是多个GaN岛，每个岛对应于给定的鳍。在某些情况下，这些技术可用于形成具有相对小的形状因数，低导通状态电阻和低截止状态泄漏的各种非平面隔离GaN晶体管架构。

29. 发明申请

WO2016204965A1 DOPED BARRIER LAYERS IN EPITAXIAL GROUP III NITRIDES 审中-公开
标题翻译：外源III族硝酸盐中的DOPED BARRIER层
公开(公告)号：WO2016204965A1
公开(公告)日：2016-12-22
申请号：PCT/US2016/034935
申请日：2016-05-31
申请人： RAYTHEON COMPANY
发明人： SCHULTZ, Brian D. , TORABI, Abbas , CHUMBES, Eduardo M. , REZA, Shahed , HOKE, William E.
IPC分类号： H01L29/778 , H01L29/36 , H01L29/20 , H01L29/207
CPC分类号： H01L21/0254 , H01L29/2003 , H01L29/207 , H01L29/36 , H01L29/7781 , H01L29/7786
摘要： A semiconductor structure having a Group III-N buffer layer (16) and a Group III-N barrier layer (18) in direct contact to form a junction (20) between the Group III-V buffer layer the Group III-N barrier layer producing a two dimensional electron gas (2DEG) channel, the Group III-N barrier layer having a varying dopant concentration. The lower region (18a) of the Group III-N barrier layer closest to the junction is void of intentionally introduced dopant and a region (18b) above the lower region has intentionally introduced dopants with a doping concentration above 1x10 17 atoms per cm 3 .
摘要翻译：一种半导体结构，其具有直接接触的III-N族缓冲层（16）和III-N族阻挡层（18），以形成III-V族缓冲层之间的III-N阻挡层产生二维电子气（2DEG）通道，III-N阻挡层具有不同的掺杂浓度。最靠近结的III-N阻挡层的下部区域（18a）没有有意引入的掺杂剂，并且在下部区域上方的区域（18b）有意地引入掺杂浓度高于1×10 17原子/ cm 3的掺杂剂。

30. 发明申请

WO2016149146A1 PARALLELING OF SWITCHING DEVICES FOR HIGH POWER CIRCUITS 审中-公开
标题翻译：大功率电路开关装置并联
公开(公告)号：WO2016149146A1
公开(公告)日：2016-09-22
申请号：PCT/US2016/022214
申请日：2016-03-11
申请人： TRANSPHORM, INC.
发明人： WANG, Zhan
IPC分类号： H03K17/12 , H03K17/16 , H03K17/64
CPC分类号： H03K17/6874 , H01L29/2003 , H01L29/7787 , H02M1/08 , H02M7/5395 , H02M2001/0054 , H02P27/08 , H03K17/122 , H03K17/162 , H03K17/164 , H03K17/64
摘要： A circuit includes first and second half bridges, a first inductor, a second inductor, and a main inductor. The half bridges each include a high side switch, a low side switch, and a gate driver configured to apply switching signals to the high side switch and the low side switch. The first inductor has one side electrically connected to an output node of the first half bridge between the high side switch and the low side switch. The second inductor has one side electrically connected to an output node of the second half bridge between the high side switch and the low side switch. The main inductor is coupled to a node between the other sides of the first and second inductors. The main inductor has a greater inductance than each of the first and second inductors, and the first and second inductors are inversely coupled to one another.
摘要翻译：电路包括第一和第二半桥，第一电感，第二电感和主电感。半桥各自包括高侧开关，低侧开关和配置为向高侧开关和低侧开关施加开关信号的栅极驱动器。第一电感器的一侧电连接到高侧开关和低侧开关之间的第一半桥的输出节点。第二电感器的一侧电连接到高侧开关和低侧开关之间的第二半桥的输出节点。主电感器耦合到第一和第二电感器的另一侧之间的节点。主电感器具有比每个第一和第二电感器更大的电感，并且第一和第二电感器彼此反向耦合。

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