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    • 27. 发明申请
    • A SEMICODUCTOR TESTING DEVICE WITH ELASTOMER INTERPOSER
    • 具有弹性体插入器的半导体测试装置
    • WO2008153558A3
    • 2009-04-09
    • PCT/US2007069896
    • 2007-05-29
    • TOUCHDOWN TECHNOLOGIES INC
    • KARKLIN KENGARABEDIAN RAFFI
    • G01R31/02
    • G01R1/0735H01L24/45H01L2224/45144H01L2924/00014H01L2924/0105H01L2924/01079H01L2924/1461H01L2224/48H01L2924/00
    • A novel device for testing semiconductor chips is disclosed A benefit with all the embodiments described herein is that the device may expepence zero (or near zero) nascent force The device may be comppsed of a printed circuit board (PCB)that has at least one PCB piercing structure, a probe contactor substrate that has at least one substrate piercing structure, wherein the substrate piercing structure is electrically connected to a probe contactor, and an interposer that has at least one electrical via made of a conductive elastomer When the PCB piercing structure and the substrate piercing structure pierce the elastomer, the PCB becomes electrically connected to the probe contactor Instead of the piercing structure, the PCB or the probe contractor substrate may be adhered to the elastomer by an adhesive, such that the PCB becomes electrically connected to the probe contactor
    • 公开了一种用于测试半导体芯片的新型器件。本文所述的所有实施例的优点在于,器件可以超过零(或近零)新生力。该器件可以由具有至少一个PCB的印刷电路板(PCB) 穿孔结构,具有至少一个基板穿孔结构的探针接触器基板,其中所述基板穿孔结构电连接到探针接触器,以及具有至少一个由导电弹性体制成的电通路的插入件当所述PCB穿孔结构和 基板刺穿结构刺穿弹性体,PCB变得电连接到探针接触器代替穿孔结构,PCB或探针承载基底可以通过粘合剂粘附到弹性体上,使得PCB变得电连接到探针 接触
    • 28. 发明申请
    • SMALL-SIZE LAYOUT FOR THE PLANAR FINAL METAL DIE ATTACH PADS OF AN INTEGRATED CIRCUIT´S CSP-TYPE SEMICONDUCTOR CHIP DEVICE ASSEMBLEY
    • 集成电路CSP型半导体芯片器件组件的平面最终金属连接板的小尺寸布局
    • WO2009022252A2
    • 2009-02-19
    • PCT/IB2008/053093
    • 2008-08-01
    • NXP B.V.SYRE, Jörg
    • SYRE, Jörg
    • H01L23/485
    • H01L23/522H01L23/3114H01L24/02H01L24/10H01L24/13H01L24/45H01L2224/0401H01L2224/13H01L2224/13099H01L2224/45124H01L2224/45144H01L2924/00014H01L2924/01006H01L2924/01013H01L2924/01014H01L2924/01022H01L2924/01028H01L2924/01029H01L2924/01033H01L2924/01047H01L2924/01049H01L2924/0105H01L2924/01073H01L2924/01074H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/01322H01L2924/014H01L2924/04953H01L2924/10329H01L2924/14H01L2924/181H01L2924/19043H01L2924/30105H01L2224/48H01L2924/00
    • The present invention is related to die bonding technology, in particular to a small- size layout for the surface areas of the planar final metal die attach pads (9) in a novel CSP-type semiconductor integrated circuit chip device assembly, wherein each planar final metal die attach pad (9) contained in this assembly layout has a surface area that is smaller in size than those of conventional semiconductor integrated circuit chips that are to be mounted on a printed circuit board's substrate in chip-scale package technology. For applications with a restricted upper tolerable limit for the total capacitance of the integrated circuit, parasitic metal-silicon capacitance, which occurs between each planar final metal die attach pad (9) and the substrate (8), is detrimental. For mechanical robust CSP products, on the other hand, it is a necessary requirement that the planar metal die attach pad area surfaces are larger in size than their associated under-bump metallization (UBM) areas (5). Reducing said parasitic metal-silicon capacitance, which can easily be achieved by using metal die attach pads (9) with smaller surface areas, is very lifetime-critical in cases where metal bonding wires (1) are required and results in that the semiconductor chip device might possibly fail during mechanical stress. A significant problem concerning the robustness of the assembly are the edges of the under-bump metallization areas (5), which is because there are usually high stress forces along these edges during the lifetime of said chip-scale packaged semiconductor chip device assembly. The present invention therefore proposes a chip-scale packaged semiconductor chip device assembly bonded onto planar final metal die attach pad layers (9) on a printed circuit board (8) by means of solder bumps, wherein the surface areas of the planar final metal die attach pad layers (9) are smaller in size than their associated under-bump metallization layers (5). For die-to-die bond wiring, very thin and hard electrically conductive materials are proposed which - according to a refinement of the present invention - may be used as surface-mounted ohmic resistors. In this case, the mechanical stability of the bump-chip connection is still given, and, at the same time, parasitic metal-silicon capacitances of the die attach pads to the substrate are reduced.
    • 本发明涉及芯片接合技术,特别涉及一种用于新型CSP型半导体集成电路芯片器件组件中的平面最终金属芯片附接焊盘(9)的表面区域的小尺寸布局,其中每个平面最终 包含在该组装布局中的金属管芯附接垫(9)的尺寸小于以芯片级封装技术安装在印刷电路板的基板上的常规半导体集成电路芯片的尺寸。 对于对于集成电路的总电容具有限制的上限容许限制的应用,在每个平面的最终金属管芯附着焊盘(9)和衬底(8)之间发生的寄生金属 - 硅电容是有害的。 对于机械坚固的CSP产品,另一方面,平面金属管芯安装焊盘区域表面的尺寸要大于其相关的凸块下金属化(UBM)区域(5)的必要要求。 通过使用具有较小表面积的金属管芯附接焊盘(9)可以很容易地实现所述寄生金属 - 硅电容的减小,在需要金属接合线(1)的情况下是非常长寿命的关键,并导致半导体芯片 装置在机械应力时可能会失效。 关于组件的鲁棒性的一个重大问题是凸起下金属化区域(5)的边缘,这是因为在所述芯片级封装半导体芯片器件组件的寿命期间通常沿着这些边缘通常具有高应力。 因此,本发明提出了一种芯片级封装的半导体芯片器件组件,其通过焊料凸块接合到印刷电路板(8)上的平面最终金属管芯附着垫层(9)上,其中平面最终金属裸片的表面积 附着垫层(9)的尺寸小于其相关的凸块下金属化层(5)。 对于管芯到管芯的接合布线,提出非常薄且硬的导电材料,根据本发明的改进,可以将其用作表面安装的欧姆电阻器。 在这种情况下,仍然给出凸块芯片连接的机械稳定性,并且同时,将芯片附着焊盘的寄生金属 - 硅电容减少到衬底。