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11. 发明申请

WO2003103314A1 SYSTEM AND METHOD FOR RETRANSMISSION OF DATA 审中-公开
标题翻译：用于数据恢复的系统和方法
公开(公告)号：WO2003103314A1
公开(公告)日：2003-12-11
申请号：PCT/US2003/015001
申请日：2003-05-13
申请人： OPENCELL, INC.
发明人： MILLAR, Jeffrey, R.
IPC分类号： H04Q7/30
CPC分类号： H04L1/0083 , H04J3/047 , H04J3/14 , H04J3/1611 , H04J2203/0028 , H04L1/1835 , H04W4/18 , H04W88/085
摘要： A received RF signal can include data information intended for transmission over a wireless communication link (160). The data information of the signal can be processed at a node (130) to produce overhead bits supporting a serial transmission of the data information over a communication medium (140) to another node (150). For example, the data information of the received signal and overhead bits can be combined or framed according to a serial transport protocol for transmission over the communication medium (140) to a target receiver (150), where the original RF signal can be reconstructed.
摘要翻译：所接收的RF信号可以包括旨在通过无线通信链路（160）传输的数据信息。可以在节点（130）处处理信号的数据信息，以产生支持通过通信介质（140）将数据信息串行传输到另一个节点（150）的开销位。例如，可以根据用于通过通信介质（140）传输到目标接收机（150）的串行传输协议来组合或成帧接收信号和开销比特的数据信息，其中可以重建原始RF信号。

12. 发明申请

WO0249248A3 DEMULTIPLEXER FOR HIGH DATA RATE SIGNALS 审中-公开
标题翻译：用于高数据速率信号的分解器
公开(公告)号：WO0249248A3
公开(公告)日：2003-01-16
申请号：PCT/US0148696
申请日：2001-12-12
申请人： AXE INC , LAGASSE MICHAEL , RAO HEMONTH , KUSHNER LARRY , KESLER MORRIS
发明人： LAGASSE MICHAEL , RAO HEMONTH , KUSHNER LARRY , KESLER MORRIS
IPC分类号： H03L7/06 , H03L7/20 , H04J3/04 , H04L1/20 , H04L7/027 , H04L7/033 , H04L7/04
CPC分类号： H04L1/206 , H03L7/06 , H03L7/20 , H04J3/047 , H04L7/027 , H04L7/033 , H04L7/048
摘要： A demultiplexer for Time Division Multiplexed (TDM) signals is described. The demultiplexer includes an electrical splitter that separates an electrical TDM data signal into multiple electrical TDM data signals. A clock recovery circuit generates a clock signal that is synchronized to the electrical TDM data signal and that has a frequency that is harmonically related to a single TDM channel data rate. A phase shifter adjusts the phase of the clock signal. The demultiplexer also includes multiple decision circuits each having a data input for receiving the electrical TDM data signal. Each of the decision circuits also has a clock input that is electrically coupled to an output of the clock recovery circuit for receiving the clock signal. Each of the decision circuits generates demultiplexed TDM signals. The phase shifter is adjusted so that the desired data in each of the demultiplexed TDM signals is selected.
摘要翻译：描述了用于时分多路复用（TDM）信号的解复用器。解复用器包括将电TDM数据信号分离成多个电TDM数据信号的电分路器。时钟恢复电路产生与电TDM数据信号同步并且具有与单个TDM信道数据速率谐波相关的频率的时钟信号。移相器调节时钟信号的相位。解复用器还包括多个判决电路，每个判定电路具有用于接收电TDM数据信号的数据输入。每个判定电路还具有电耦合到时钟恢复电路的输出的时钟输入，用于接收时钟信号。每个判决电路产生解复用的TDM信号。调整移相器以便选择每个解复用TDM信号中的期望数据。

13. 发明申请

WO1996038943A1 DEMULTIPLEXER, A PROTECTION SWITCH UNIT, A TELECOMMUNICATION NETWORK AND A METHOD OF DEMULTIPLEXING 审中-公开
标题翻译：解复用器，保护开关单元，电信网络和解复用方法
公开(公告)号：WO1996038943A1
公开(公告)日：1996-12-05
申请号：PCT/SE1996000679
申请日：1996-05-24
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ) , BLADH, Mats
发明人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)
IPC分类号： H04J03/14
CPC分类号： H04J3/047 , H03K17/6285 , H04J3/14
摘要： A demultiplexer which in a demultiplexing process selects an output for a signal received on input, a protection switch unit which includes one such demultiplexer and a telecommunications network which includes one such protection switch unit, wherein the demultiplexer has an input (IN+, IN-) and at least two outputs (OUT1+, OUT1-, OUT2+, OUT2-). A first connection point (IN1+) in the input is connected to a first transmission line (TLINE_1) for conducting an input signal thereto. A first connection point (OUT1+, OUT2+) in each output is connected to the transmission line (TLINE_1) via a respective first controllable signal forwarding device (Q1, Q2). An externally controllable signal switch means (S1, S2) is also connected to each output. A switch means (S1) controls one of said first signal forward devices (Q1) to forward the signal that is applied over the first transmission line (TLINE_1) to the first connection point (OUT1+) in a selected output.
摘要翻译：一种解复用器，其在多路分解处理中选择输入端用于输入的信号，保护开关单元，包括一个这样的解复用器和包括一个这样的保护开关单元的电信网络，其中多路分解器具有输入（IN +，IN-）和至少两个输出（OUT1 +，OUT1-，OUT2 +，OUT2-）。输入端的第一连接点（IN1 +）连接到第一传输线（TLINE_1），用于向其输入信号。每个输出端的第一连接点（OUT1 +，OUT2 +）经由相应的第一可控信号转发装置（Q1，Q2）连接到传输线（TLINE_1）。外部可控信号开关装置（S1，S2）也连接到每个输出端。开关装置（S1）控制所述第一信号转发装置（Q1）中的一个，以将在第一传输线（TLINE_1）上施加的信号转发到所选输出中的第一连接点（OUT1 +）。

14. 发明申请

WO1995010904A1 SIGNAL PROCESSING UNIT 审中-公开
标题翻译：信号处理单元
公开(公告)号：WO1995010904A1
公开(公告)日：1995-04-20
申请号：PCT/SE1994000910
申请日：1994-10-03
申请人： TELEFONAKTIEBOLAGET LM ERICSSON
发明人： TELEFONAKTIEBOLAGET LM ERICSSON , BUHRGARD, Karl, Sven, Magnus , HAULIN, Tord, Lennart
IPC分类号： H04L07/04
CPC分类号： H04J3/047 , H04J3/0632 , H04J3/0685 , H04L2012/5674 , H04Q11/0478
摘要： A signal processing unit (1) in which incoming bit-position carrying signals (2') are time-controlled in relation to a first clock signal (3), and wherein outgoing bit-position carrying signals (4) are time-controlled exactly in relation to said first clock signal (3), and wherein signal processing procedures carried out internally in the unit (1) require the presence of the bit positions of the signal (2') and the clock pulses of a clock signal (3'). The signal processing carried out internally in the unit (1, 20) is controlled by the clock pulses of a second clock signal (3') which has the same frequency as the first clock signal (3). The synchronization required for the internal signal processing is achieved in a unit (13) by changing the time-relationship of the clock pulses of the second clock signal (3') to synchronism with the bit positions of the signals (2'); in that the thus processed data signals (4') can be stored in buffer circuits (10), wherein a time-controlled relationship belonging to the process signals (4') can be changed to synchronism with the clock pulses (3a, 3b) of the first clock signals (3) before they appear as outgoing signals (4).
摘要翻译：一种信号处理单元（1），其中输入位位置传送信号（2'）相对于第一时钟信号（3）被时间控制，并且其中输出位位置传送信号（4）精确地被时间控制相对于所述第一时钟信号（3），并且其中在单元（1）内部执行的信号处理过程需要信号（2'）的位位置和时钟信号（3'）的时钟脉冲的存在，）。在单元（1,20）内部执行的信号处理由与第一时钟信号（3）具有相同频率的第二时钟信号（3'）的时钟脉冲控制。通过将第二时钟信号（3'）的时钟脉冲的时间关系改变为与信号（2'）的位位置同步，在单元（13）中实现内部信号处理所需的同步; 因为这样处理的数据信号（4'）可以存储在缓冲电路（10）中，其中属于处理信号（4'）的时间控制关系可以改变为与时钟脉冲（3a，3b）同步，的第一时钟信号（3）在出现为输出信号（4）之前。

15. 发明申请

WO1995002951A1 SERIAL BIT RATE CONVERTER FOR A TDM SWITCHING MATRIX 审中-公开
标题翻译：用于TDM交换矩阵的串行比特率转换器
公开(公告)号：WO1995002951A1
公开(公告)日：1995-01-26
申请号：PCT/CA1994000377
申请日：1994-07-13
申请人： MITEL CORPORATION , SKIERSZKAN, Simon , LEHMANN, Jim
发明人： MITEL CORPORATION
IPC分类号： H04Q11/08
CPC分类号： H04J3/047 , H04Q11/08
摘要： A time division switching matrix capable of effecting rate conversion comprises a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of serial outputs for connection to respective serial output links, each capable of carrying time division multiplexed PCM channels, and a serial-to-parallel converter associated with each input for converting a serial input stream to parallel format, each said serial-to-parallel converter being independently configurable to produce the same net parallel throughput regardless of the bit rate of the associated input link. The output side of the switching matrix can be similarly configured.
摘要翻译：能够进行速率转换的时分切换矩阵包括用于连接到相应的串行输入链路的多个串行输入，每个串行输入链路能够承载时分复用PCM信道，多个串行输出用于连接到相应的串行输出链路，携带时分复用PCM信道，以及与每个输入相关联的串行到并行转换器，用于将串行输入流转换为并行格式，每个所述串行到并行转换器可独立配置以产生相同的并行吞吐量，而不管相关输入链路的比特率。可以类似地配置开关矩阵的输出侧。

16. 发明申请

WO1994000934A1 HIGH-SPEED TIME-MULTIPLEXED DATA TRANSMISSION SYSTEM 审中-公开
标题翻译：高速时间多路复用数据传输系统
公开(公告)号：WO1994000934A1
公开(公告)日：1994-01-06
申请号：PCT/US1993005733
申请日：1993-06-15
申请人： BAXTER DIAGNOSTICS INC.
发明人： BAXTER DIAGNOSTICS INC. , KRAFT, Clifford, H.
IPC分类号： H04J03/04
CPC分类号： H04J3/047
摘要： A high-speed burst digital time multiplexed data system has N parallel input data paths that are multiplexed onto a serial data path for transmission from a transmitter to a receiver. Serial transmission takes place in a short burst upon command at the transmitter. Data from the serial data path is demultiplexed back into N parallel data paths at the receiver. The entire process is accomplished asynchronously without the aid of a clock or framing signal. In the preferred embodiment, a train of N sampling pulses is generated by two tapped delay lines, one at the transmitter and one of the receiver. The length of each sequential sampling pulse is determined by the tap spacing of the delay line, and the duration of the entire burst process is equal to the total delay of the delay line. A new burst may be initiated at any time after the completion of the previous burst. Thus, bursts may follow each other immediately or be arbitrarily spaced to occur whenever data transmission is required.
摘要翻译：高速脉冲串数字时间复用数据系统具有N个并行输入数据路径，其被复用到串行数据路径上，用于从发射机到接收机的传输。串行传输在发射机的命令中以短脉冲串发生。来自串行数据路径的数据在接收机被解复用为N个并行数据路径。整个过程是不经过时钟或帧信号的异步完成的。在优选实施例中，通过两个抽头延迟线产生一列N个采样脉冲，一个在发射机和一个接收机之间。每个顺序采样脉冲的长度由延迟线的抽头间距确定，并且整个突发处理的持续时间等于延迟线的总延迟。可以在完成先前的突发之后的任何时间启动新的突发。因此，当需要数据传输时，突发可以立即彼此跟随或任意间隔。

17. 发明申请

WO2017189497A1 HIGH SPEED SERIALIZER USING QUADRATURE CLOCKS 审中-公开
标题翻译：高速串行器使用快速时钟
公开(公告)号：WO2017189497A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/029278
申请日：2017-04-25
申请人： MACOM CONNECTIVITY SOLUTIONS, LLC
发明人： GUPTA, Vijay , GUPTA, Tarun
IPC分类号： H04L7/04 , H04L7/00 , H04L25/02
CPC分类号： H04J3/0691 , H03M9/00 , H04J3/047 , H04J3/0682 , H04J3/0685 , H04L7/0037
摘要： Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.
摘要翻译：技术使用正交时钟高效地串行化多个数据流。串行器采用第一，第二，第三和第四时钟信号。串行器经由寄存器接收多个数据流，其中四个路径中的每一个包括寄存器，缓冲器和开关，第一和第四路径的寄存器与第三时钟信号相关联，并且第二和第三路径的寄存器与第一时钟信号相关联，并且与与第一时钟信号相关联的第一和第四路径的开关以及与第三时钟信号相关联的第二和第三路径的开关。第一和第二路径的开关经由另一缓冲器将相应的数据位传送到第五开关，其中第五开关与时间延迟分量（TDC）的延迟的第二时钟信号相关联。第三和第四路径的开关经由另一缓冲器将相应的数据位传送到第六开关，其中第六开关与TDC的延迟的第四时钟信号相关联。

18. 发明申请

WO2013139033A1 CONFIGURABLE MULTI-MODE MEDIA INDEPENDENT INTERFACE 审中-公开
标题翻译：可配置的多模式媒体独立接口
公开(公告)号：WO2013139033A1
公开(公告)日：2013-09-26
申请号：PCT/CN2012/072898
申请日：2012-03-23
申请人： QUALCOMM INCORPORATED , YU, Hongchun
发明人： YU, Hongchun
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H04J3/047 , H04J3/0697 , H04L25/4908 , H04L41/0803 , H04L69/18
摘要： A configurable media independent interface in an integrated circuit device includes a first plurality of channels and a second plurality of channels, wherein each channel of the first and second pluralities includes a transmit path. The interface also includes a first serializer configurable to serialize transmit data for the first and second pluralities of channels in a first mode and to serialize transmit data for the first plurality of channels in a second mode, and a second serializer configurable to be disabled in the first mode and to serialize data for the second plurality of channels in the second mode.
摘要翻译：集成电路设备中的可配置媒体独立接口包括第一多个信道和第二多个信道，其中第一和第二多个信道的每个信道包括发送路径。该接口还包括可配置为以第一模式串行化用于第一和第二多个信道的发送数据的第一串行器，并且以第二模式串行化第一多个信道的发送数据，以及可配置为在第二模式中被禁用的第二串行器并且在第二模式中串行化第二多个信道的数据。

19. 发明申请

WO2012041852A2 RF DIVIDER USING DIRECT DIGITAL SYNTHESIS 审中-公开
标题翻译： RF分离器使用直接数字合成
公开(公告)号：WO2012041852A2
公开(公告)日：2012-04-05
申请号：PCT/EP2011/066769
申请日：2011-09-27
申请人： ST-ERICSSON SA , MATEMAN, Paul , HESEN, Leonardus , FRAMBACH, Johannes
发明人： MATEMAN, Paul , HESEN, Leonardus , FRAMBACH, Johannes
CPC分类号： H03K23/665 , H03K23/68 , H03M9/00 , H04J3/047 , H04J3/0685
摘要： An RF divider directly synthesizes a desired RF as a digital pattern that can be programmed and output at a VCO frequency. An exemplary RF divider comprises a pre-sequencer and a parallel-to-serial converter. The pre-sequencer successively outputs consecutive M-bit sections of a parallel word, where the parallel word comprises one or more copies of a frequency dividing bit pattern defining a frequency divisor. The parallel-to-serial converter performs a parallel-to-serial conversion on the M-bit sections of the parallel word based on the fixed radio frequency to generate an output signal having the desired radio frequency, where the output signal comprises a serial bit stream of the parallel word.
摘要翻译： RF分频器直接将期望的RF合成为数字码型，可以在VCO频率下进行编程和输出。示例性的RF分配器包括预定序器和并串转换器。预定序器连续地输出并行字的连续的M位段，其中并行字包括定义频率除数的分频位模式的一个或多个副本。并行到串行转换器基于固定射频在并行字的M位部分上执行并行到串行转换以生成具有期望射频的输出信号，其中输出信号包括串行比特平行词的流。

20. 发明申请

WO2011152818A1 MULTIPLEXED SERIAL MEDIA INDEPENDENT INTERFACE 审中-公开
标题翻译：多重串行媒体独立接口
公开(公告)号：WO2011152818A1
公开(公告)日：2011-12-08
申请号：PCT/US2010/036831
申请日：2010-06-01
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , DOVE, Daniel, J.
发明人： DOVE, Daniel, J.
IPC分类号： H04L29/10 , H04L12/56
CPC分类号： H04J3/047 , H04L12/40136 , H04L29/10 , H04L69/14
摘要： Systems, methods, and devices are provided for a multiplexed serial media independent interface (110-1, 110-N, 210). One system for handling data includes a physical layer (PHY) circuit (102-1, 102-N, 202-1, 202-N) operating at a first rate including a number of ports (104-1, 104-P), a media access control (MAC) circuit (108, 208-1, 208-N) operating at the first rate including a number of ports, and a multiplexed serial media independent interface (110-1, 110-N, 210) between the MAC circuit (108, 208-1, 208-N) and the PHY circuit (102-1, 102-N, 202-1, 202-N) operating at a second rate, which is greater than the first rate. The interface (110-1, 110-N, 210) includes a number of conductors and is configured to communicate data between the MAC circuit (108, 208-1, 208-N) and the PHY circuit (102-1, 102-N, 202-1, 202-N) via four conductors per up to eight ports (104-1, 104-P) of the PHY circuit (102-1, 102-N, 202-1, 202-N).
摘要翻译：系统，方法和设备被提供用于多路复用串行媒体无关接口（110-1,110-N，210）。一种用于处理数据的系统包括以包括多个端口（104-1,104-P）的第一速率操作的物理层（PHY）电路（102-1,102-N，202-1,202-N）以包括多个端口的第一速率操作的媒体访问控制（MAC）电路（108,208-1,208-N），以及在多个串行媒体无关的接口（110-1,110-N，210）之间 MAC电路（108,208-1,208-N）和以大于第一速率的第二速率操作的PHY电路（102-1,102-N，202-1,202-N）。接口（110-1,110-N，210）包括多个导体，并且被配置为在MAC电路（108,208-1,208-N）和PHY电路（102-1,102- N，202-1,202-N）经由每个至多八个PHY电路（102-1,102-N，202-1,202-N）的八个端口（104-1,104-P）的四个导体。

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