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11. 发明申请

WO03017336A3 DRAM TRENCH CAPACITOR AND METHOD OF MAKING THE SAME 审中-公开
标题翻译： DRAM TRENCH电容器及其制造方法
公开(公告)号：WO03017336A3
公开(公告)日：2003-09-04
申请号：PCT/US0225680
申请日：2002-08-13
申请人： AMBERWAVE SYSTEMS CORP
发明人： BULSARA MAYANK , CURRIE MATTHEW T , LOCHTEFELD ANTHONY J
IPC分类号： H01L21/8242 , H01L29/94 , H01L27/108
CPC分类号： H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/10897 , H01L28/40 , H01L29/1054 , H01L29/7849 , H01L29/945
摘要： In accordanse with the present invention, DRAM trench capacitors are formed in substrates including materials other than Si, such as SiGe. These materials may be relaxed or strained, and may have dislocation defects. In one aspect, therefore, the invention features a method for forming a trench capacitor in a semiconductor substrate. A trench is defined extending into the semiconductor substrate from a top surface of the substrate. A first conductive material is deposited in the trench to define an outer plate, and an insulating layer is formed on the outer plate. A second conductive material is deposited in the trench to define an inner plate. Trench capacitors formed in accordance with the present invention may be utilized in conventional CMOS logic circuits. A DRAM trench capacitor (600) is formed on a semiconductor substrate (610) in accordance with any of the methods described above. Semiconductor substrate (610) includes a substrate (612) formed of, e.g., Si, and a layer (614) including, for example, graded and relayed and relaxed SiGe layers. A tensilely strained layer (616) is disposed over layer (614). DRAM trench capacitor (600) is in electrical communication with access transistor (620). A CMOS logic circuit (630) is also formed on semiconductor substrate (610). CMOS logic circuit (630) may include an NMOS transistor (640) and a PMOS transistor (650), with each transistor having a channel (660, 670) disposed in tensilely strained layer (616).
摘要翻译：根据本发明，DRAM沟槽电容器形成在包括除Si之外的材料的衬底中，例如SiGe。这些材料可能松弛或变形，并且可能具有位错缺陷。因此，一方面，本发明的特征在于在半导体衬底中形成沟槽电容器的方法。限定从衬底的顶表面延伸到半导体衬底中的沟槽。第一导电材料沉积在沟槽中以限定外板，并且在外板上形成绝缘层。第二导电材料沉积在沟槽中以限定内板。根据本发明形成的沟槽电容器可以用于传统的CMOS逻辑电路中。根据上述任何一种方法，在半导体衬底（610）上形成DRAM沟槽电容器（600）。半导体衬底（610）包括由例如Si形成的衬底（612）和包括例如渐变和中继且弛豫的SiGe层的层（614）。拉伸应变层（616）设置在层（614）之上。 DRAM沟槽电容器（600）与存取晶体管（620）电连通。 CMOS逻辑电路（630）也形成在半导体衬底（610）上。 CMOS逻辑电路（630）可以包括NMOS晶体管（640）和PMOS晶体管（650），每个晶体管具有设置在拉伸应变层（616）中的沟道（660,670）。

12. 发明申请

WO01017032A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容器结构
公开(公告)号：WO01017032A1
公开(公告)日：2001-03-08
申请号：PCT/EP2000/008307
申请日：2000-08-25
IPC分类号： H01L29/94
CPC分类号： H01L24/05 , H01L24/48 , H01L29/945 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05624 , H01L2224/05644 , H01L2224/4807 , H01L2224/4845 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/19041 , H01L2224/45099
摘要： The invention relates to a capacitor structure, comprising a capacitor region, a border region and optionally comprising a contact region. Said capacitor region has a first conductive layer (1), a continuous first insulation layer which is applied to the first conductive layer and a continuous second conductive layer (6) which is applied to the insulation layer (5). In addition, elongated recesses are incorporated into the capacitor region. The capacitor structure is characterised in that the second insulation layer (7) is located either between the first electrically conductive layer and the first insulation layer, or between the first electrically conductive layer and the second electrically conductive layer.
摘要翻译：本发明涉及一种具有电容器区域，边缘区域和可能的接触区域，其中，在所述电容器区域中，第一导电层（1），负载通过第一绝缘层和在绝缘层上施加到第一导电层的电容器结构（5）连续地施加第二导电层（6）存在时，其特征在于，进一步延长凹部在所述电容器区域中，其特征在于，引入所述第二绝缘层（7）任一所述第一导电层和第一绝缘层之间或所述第一导电层和第二导电之间层。

13. 发明申请

WO9856020A3 METHOD FOR ARRANGEMENT OF A BURIED CAPACITOR, AND A BURIED CAPACITOR ARRANGED ACCORDING TO SAID METHOD 审中-公开
标题翻译：用于布置电容器的布置方法和根据公式方法安排的电容器
公开(公告)号：WO9856020A3
公开(公告)日：1999-03-04
申请号：PCT/SE9801063
申请日：1998-06-04
申请人： ERICSSON TELEFON AB L M
发明人： LARSSON TORBJOERN , JOENSSON JONAS
IPC分类号： H01L27/04 , H01L21/822 , H01L29/94 , H01G4/33
CPC分类号： H01L29/945
摘要： The present invention relates to a method for arrangement of a buried capacitor on a substrate or the like, and a buried capacitor arranged according to the method. In order to diminish the resistive losses in a capacitor and to make it more efficient, in semiconductor circuits, instead of the polycrystalline layer, one or more bodies (14) of metal such as aluminium or tungsten may be used. This has been made possible using a new technique in which a trench filling consisting of conducting material is etched away without removal through etching of the insulating layer (13) in the trench. After the removal through etching of the trench filling, the trench is filled using the metal (14) as above, whereby the insulating layer (13) between the conducting material and the metal body will separate two conducting surfaces, thereby forming the buried capacitor.

14. 发明申请

WO8700690A3 HIGH-PERFORMANCE DRAM ARRAYS INCLUDING TRENCH CAPACITORS 审中-公开
标题翻译：高性能DRAM阵列包括TRENCH电容器
公开(公告)号：WO8700690A3
公开(公告)日：1987-07-30
申请号：PCT/US8601426
申请日：1986-07-08
申请人： AMERICAN TELEPHONE & TELEGRAPH
发明人： LYNCH WILLIAM THOMAS
IPC分类号： G11C11/401 , H01L21/76 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10861 , H01L27/10829 , H01L29/945
摘要： Parallel elongated trenches (22) in a silicon substrate (11, 12) are utilized to form multiple distinct memory cell capacitors on each continuous wall (24, 26) of each trench. Chanstops (52) are formed between adjacent capacitors to achieve electrical isolation. A separate word line (64) overlies each trench wall and is connected via respective MOS transistors to the spaced-apart capacitors formed on the wall. A reliable high-density memory characterized by excellent performance is thereby realized.

15. 发明申请

WO8700690A2 HIGH-PERFORMANCE DRAM ARRAYS INCLUDING TRENCH CAPACITORS 审中-公开
标题翻译：高性能DRAM阵列包括TRENCH电容器
公开(公告)号：WO8700690A2
公开(公告)日：1987-01-29
申请号：PCT/US8601426
申请日：1986-07-08
申请人： AMERICAN TELEPHONE & TELEGRAPH
发明人： LYNCH WILLIAM THOMAS
IPC分类号： G11C11/401 , H01L21/76 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10861 , H01L27/10829 , H01L29/945
摘要： Parallel elongated trenches (22) in a silicon substrate (11, 12) are utilized to form multiple distinct memory cell capacitors on each continuous wall (24, 26) of each trench. Chanstops (52) are formed between adjacent capacitors to achieve electrical isolation. A separate word line (64) overlies each trench wall and is connected via respective MOS transistors to the spaced-apart capacitors formed on the wall. A reliable high-density memory characterized by excellent performance is thereby realized.
摘要翻译：在硅衬底（11,12）中的平行延长的沟槽（22）用于在每个沟槽的每个连续壁（24,26）上形成多个不同的存储单元电容器。在毗邻的电容器之间形成节流阀（52）以实现电气隔离。单独的字线（64）覆盖每个沟槽壁，并且经由各个MOS晶体管连接到形成在壁上的间隔开的电容器。从而实现了性能优异的可靠的高密度存储器。

16. 发明申请

WO1987000684A1 FORMING THICK DIELECTRIC AT THE BOTTOMS OF TRENCHES UTILIZED IN INTEGRATED-CIRCUIT DEVICES 审中-公开
标题翻译：在集成电路设备中使用的电缆底部形成厚度很大的电介质
公开(公告)号：WO1987000684A1
公开(公告)日：1987-01-29
申请号：PCT/US1986001472
申请日：1986-07-09
申请人： AMERICAN TELEPHONE & TELEGRAPH COMPANY
发明人： AMERICAN TELEPHONE & TELEGRAPH COMPANY , LYNCH, William, Thomas , SEIDEL, Thomas, Edward
IPC分类号： H01L21/306
CPC分类号： H01L21/306 , H01L21/31654 , H01L21/76232 , H01L29/945
摘要： Selective wet or plasma anodization is utilized for forming a relatively thick dielectric layer (34) only at the bottoms of trenches (10) included in semiconductor, integrated devices. In that way, the electrical characteristics of trenches that include bottoms having surface roughness and/or sharp or irregular corners are significantly improved. Additionally, electrically isolated capacitor structures in elongated trenches are made feasible.

17. 发明申请

WO8603333A2 HIGH-PERFORMANCE TRENCH CAPACITORS FOR DRAM CELLS 审中-公开
标题翻译：用于DRAM电池的高性能TRENCH电容器
公开(公告)号：WO8603333A2
公开(公告)日：1986-06-05
申请号：PCT/US8502234
申请日：1985-11-11
申请人： AMERICAN TELEPHONE & TELEGRAPH
发明人： LEBOWITZ JOSEPH , LYNCH WILLIAM THOMAS
IPC分类号： H01L27/04 , G11C11/34 , G11C11/403 , H01L21/225 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10861 , H01L21/2257 , H01L29/945 , Y10S148/109
摘要： A trench version of a high-capacitance (Hi-C) capacitor for a dynamic random-access-memory (DRAM) cell is made utilizing a doping technique. A shallow highly doped trench region is thereby formed. At the same time, selected lateral surface portions (24) of the structure are also thereby highly doped. These surface portions permit a direct electrical connection to be easily made between the capacitor and a subsequently formed adjacent access transistor.

18. 发明申请

WO2017041936A1 GRABENKONDENSATOR UND VERFAHREN ZUR HERSTELLUNG EINES GRABENKONDENSATORS 审中-公开
标题翻译：抓斗电容器及其制造方法的沟槽式电容器
公开(公告)号：WO2017041936A1
公开(公告)日：2017-03-16
申请号：PCT/EP2016/066850
申请日：2016-07-15
申请人： ROBERT BOSCH GMBH
发明人： SCHWAIGER, Stephan , BANZHAF, Stephanie
IPC分类号： H01L29/94 , H01L49/02
CPC分类号： H01L29/945 , H01L29/66181
摘要： Verfahren zur Herstellung eines Grabenkondensators (2) mit den Schritten Bereitstellen eines Substrats (200), welches eine Vorderseite (201) und eine Rückseite (202) aufweist, Erzeugen einer Gräben (210) aufweisenden Grabenstruktur auf der Vorderseite (201) des Substrats (200), Aufbringen einer Struktur (240) auf der Rückseite (202) des Substrats (200), Abscheiden einer isolierenden dielektrischen Schicht (220) auf der Vorderseite (201) und in den Gräben (210) des Substrats (200), Aufbringen einer ersten Elektrode (230) auf die auf der Vorderseite (201) des Substrats (200) und in der Grabenstruktur (210) abgeschiedene isolierende dielektrische Schicht (220), Aufbringen einer zweiten Elektrode (250) auf die mit der Struktur (240) versehene Rückseite (202) des Substrats (200) wobei die Struktur (240) Durchbrüche (245) aufweist, so dass die zweite Elektrode (250) im Bereich der Durchbrüche (245) die Rückseite (202) des Substrats (200) kontaktiert und Halbleiter-Graben- Kondensator (2).
摘要翻译：为一个严重的电容器（2），其包括提供具有前（201）和一个背面（202）的衬底（200）的步骤的制备具有在所述基板的前侧（201）的严重结构（A过程中，产生一个沟槽（210）200 ），在基板（200）的背面（202）上施加结构（240），沉积在所述前面（201的绝缘介电层（220）），并在所述衬底（200）的沟槽（210），将第一对在基板（200）的前侧（201）和在严重结构电极（230）（210）沉积的绝缘介电层（220），上（240）提供回的结构上沉积第二电极（250）（基板的202）（200），其中，所述结构（240）（245）具有开口，使得在所述孔的区域中的第二电极（250）（245）接触所述基板（200）和半导体沟槽的后表面（202）电容器（2）。

19. 发明申请

WO2016065308A1 NANOSHAPE PATTERNING TECHNIQUES THAT ALLOW HIGH-SPEED AND LOW-COST FABRICATION OF NANOSHAPE STRUCTURES 审中-公开
标题翻译：纳米结构的高速和低成本纳米结构的纳米技术
公开(公告)号：WO2016065308A1
公开(公告)日：2016-04-28
申请号：PCT/US2015/057196
申请日：2015-10-23
申请人： BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
发明人： SREENIVASAN, Sidlgata, V. , CHERALA, Anshuman , CHOPRA, Meghali , BONNECAZE, Roger , ABED, Ovadia , YIN, Bailey , MALLAVARAPU, Akhila , SINGHAL, Shrawan , GAWLIK, Brian
IPC分类号： C03C15/00
CPC分类号： H01L21/02521 , B81C1/00031 , B81C2201/0187 , B82Y40/00 , G03F7/0002 , G11B5/746 , H01L21/02381 , H01L21/02617 , H01L21/3086 , H01L29/945 , Y10S977/887 , Y10S977/888 , Y10S977/89
摘要： A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub- 10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.
摘要翻译：一种超精密纳米尺寸模板制作方法。使用电子束光刻在基板上形成具有平滑形状（例如圆形横截面支柱）的结构。这些结构经历了与导电膜沉积交错的介质的原子层沉积，导致具有超过10nm分辨率的电子束分辨能力的特征的纳米级锐利形状。使用J-FIL进行纳米级锐利形状的抗蚀刻印刷。将纳米级尖锐形状蚀刻到基底上的下面的功能膜中，形成具有包括尖角和/或超小间隙的纳米尖锐形状的纳米成形模板。以这种方式，尖锐的形状可以保持在纳米级。此外，以这种方式，可以在纳米尺度上发生基本的纳米尺度结构（例如点和线）之外的新颖形状的基于压印的形状控制。

20. 发明申请

WO2015144755A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容结构
公开(公告)号：WO2015144755A1
公开(公告)日：2015-10-01
申请号：PCT/EP2015/056380
申请日：2015-03-25
申请人： IPDIA
发明人： VOIRON, Frédéric , TENAILLEAU, Jean-René
IPC分类号： H01L23/64 , H01L29/66 , H01L25/065 , H01L25/07 , H01L49/02 , H01L23/522
CPC分类号： H01L28/91 , H01L25/074 , H01L28/65 , H01L28/75 , H01L29/66181 , H01L29/945 , H01L2224/16145
摘要： The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a double double Metal Insulator Metal trench capacitor (10) including a basis electrode (12), an insulator layer (16, 20), a second and a third conductive layers (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to the second conductive layer (18), said second conductive layer (18) being flush with or protruding from the opposite second side (8).
摘要翻译：本发明涉及一种包括具有第一和第二侧面（6,8）的硅衬底（4）的电容器结构（2），包括基极（12）的双重双金属绝缘体金属沟槽电容器（10），绝缘体层（16,20），第二和第三导电层（18,22）; 并且包括耦合到所述基础电极（12）的第二焊盘（26）和第四焊盘（30），耦合在一起的第一焊盘（24）和第三焊盘（28），所述第一焊盘（24）与第二垫（26）相同的衬底侧，第三衬垫（28）位于与第四衬垫（30）相同的衬底侧上，第三衬垫（28）与第二导电层（18）耦合，所述第二衬垫第二导电层（18）与相对的第二侧（8）齐平或突出。

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