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11. 发明申请

WO2015041743A1 HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION 审中-公开
标题翻译：高比例记忆孔通道接触形成
公开(公告)号：WO2015041743A1
公开(公告)日：2015-03-26
申请号：PCT/US2014/047480
申请日：2014-07-21
申请人： SANDISK TECHNOLOGIES, INC.
发明人： PACHAMUTHU, Jayavel , ALSMEIER, Johann , MAKALA, Raghuveer S. , LEE, Yao-Sheng
IPC分类号： H01L27/115
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.
摘要翻译：一种制造诸如三维单片NAND存储器串的半导体器件的方法包括在衬底上的第一栅极绝缘层上蚀刻选择栅电极以形成开口，在第二栅极绝缘层的侧壁上形成第二栅极绝缘层开口，在开口的侧壁上的第二栅极绝缘层上形成牺牲间隔层，并且在开口的底表面上蚀刻第一栅极绝缘层以暴露衬底，去除牺牲间隔层以暴露第二栅极绝缘在开口的侧壁上方形成包括半导体材料在内的突起并与衬底接触的突起，其中第二栅极绝缘层位于选择栅电极与突起的第一和第二侧表面之间。

12. 发明申请

WO2016064508A2 THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF 审中-公开
标题翻译：三维NAND串存储器件及其制造方法
公开(公告)号：WO2016064508A2
公开(公告)日：2016-04-28
申请号：PCT/US2015/051242
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES, INC.
发明人： PACHAMUTHU, Jayavel , ALSMEIER, Johann , CHIEN, Henry
IPC分类号： H01L21/28
CPC分类号： H01L27/11556 , H01L21/02164 , H01L21/0217 , H01L21/02244 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/02667 , H01L21/02672 , H01L21/28273 , H01L21/28282 , H01L21/28556 , H01L21/28568 , H01L21/31111 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L29/42328 , H01L29/42344 , H01L29/4916 , H01L29/4966 , H01L29/7883
摘要： Monolithic three-dimensional NAND memory strings and methods of fabricating a monolithic three-dimensional NAND memory string include forming single crystal or large grain polycrystalline semiconductor material charge storage regions by a metal induced crystallization process. In another embodiment, a plurality of front side recesses are formed having a concave-shaped surface and a blocking dielectric and charge storage regions are formed within the front side recesses and over the concave-shaped surface. In another embodiment, layers of oxide material exposed in a front side opening of a material layer stack are surface nitrided and etched to provide convexly-rounded corner portions, and a blocking dielectric is formed over the convexly-rounded corner portions.
摘要翻译：单片三维NAND存储器串和制造单片三维NAND存储器串的方法包括通过金属诱导结晶工艺形成单晶或大晶粒多晶半导体材料电荷存储区。在另一个实施例中，形成具有凹形表面和阻挡电介质的多个前侧凹槽，并且在前侧凹槽内和凹形表面上方形成电荷存储区域。在另一个实施例中，暴露在材料层堆叠的前侧开口中的氧化物材料层被表面氮化并被蚀刻以提供凸起圆角部分，并且在凸起圆角部分上形成阻挡电介质。

13. 发明申请

WO2016053557A1 ALTERNATING REFRACTIVE INDEX IN CHARGE-TRAPPING FILM IN THREE-DIMENSIONAL MEMORY 审中-公开
标题翻译：三维存储器中电荷捕捉膜中的替代折射率
公开(公告)号：WO2016053557A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/048000
申请日：2015-09-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： PANG, Liang , DONG, Yingda , PACHAMUTHU, Jayavel
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/1052 , H01L27/1157 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： Techniques for fabricating a three-dimensional, charge-trapping memory device with improved long term data retention, and a corresponding three-dimensional, charge-trapping memory device including a stack of alternating word line layers and dielectric layers. A charge-trapping layer is deposited in a memory hole. The refractive index of portions of the charge-trapping layer adjacent to the word line layers is increased relative to the refractive index of portions of the charge-trapping layer which are adjacent to the dielectric layers. This can be achieved by doping the portions of the charge-trapping layer adjacent to the word line layers. In one approach, the charge-trapping layer is SiON doped with Si or N. In another approach, the charge-trapping layer is HfO doped with Hf. In another approach, the charge-trapping layer is HfSiON doped with Hf, Si or N.
摘要翻译：用于制造具有改进的长期数据保留的三维电荷捕获存储器件以及相应的三维电荷捕获存储器件的技术，其包括交替的字线层和电介质层的堆叠。电荷捕获层沉积在存储器孔中。与字线层相邻的电荷俘获层的部分的折射率相对于与电介质层相邻的电荷俘获层的部分的折射率增加。这可以通过掺杂与字线层相邻的电荷俘获层的部分来实现。在一种方法中，电荷捕获层是掺杂有Si或N的SiON。在另一种方法中，电荷俘获层是掺杂有Hf的HfO。在另一种方法中，电荷俘获层是掺杂有Hf，Si或N的HfSiON。

14. 发明申请

WO2016048682A2 VERTICAL MEMORY DEVICE WITH BIT LINE AIR GAP 审中-公开
标题翻译：具有位线空气隙的垂直存储器件
公开(公告)号：WO2016048682A2
公开(公告)日：2016-03-31
申请号：PCT/US2015/049597
申请日：2015-09-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： RABKIN, Peter , XIA, Jilin , PACHAMUTHU, Jayavel
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/02381 , H01L21/76802 , H01L21/7682 , H01L21/76877 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L2924/0002 , H01L2924/00
摘要： A structure includes a three-dimensional semiconductor device including a plurality of unit device structures located over a substrate. Each of the unit device structures includes a semiconductor channel including at least a portion extending vertically along a direction perpendicular to a top surface of the substrate, and a drain region contacting a top end of the semiconductor channel. The structure also includes a combination of a plurality of contact pillars and a contiguous volume that laterally surrounds the plurality of contact pillars. The plurality of contact pillars is in contact with the drain regions, and the contiguous volume has a dielectric constant less than 3.9.
摘要翻译：一种结构包括三维半导体器件，其包括位于衬底上方的多个单元器件结构。每个单元器件结构包括半导体沟道，该半导体沟道至少包括沿垂直于衬底顶表面的方向垂直延伸的部分，以及与半导体沟道顶端接触的漏极区。该结构还包括多个接触柱和横向围绕多个接触柱的连续体积的组合。多个接触柱与漏区接触，连续体的介电常数小于3.9。

15. 发明申请

WO2015134632A1 METAL REPLACEMENT PROCESS FOR LOW RESISTANCE SOURCE CONTACTS IN 3D NAND 审中-公开
标题翻译：金属替代流程中的低电阻源联系在3D NAND
公开(公告)号：WO2015134632A1
公开(公告)日：2015-09-11
申请号：PCT/US2015/018774
申请日：2015-03-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： BAENNINGER, Matthias , ALSMEIER, Johann , MATSUDAIRA, Akira , PACHAMUTHU, Jayavel
IPC分类号： H01L27/115
CPC分类号： H01L21/28282 , H01L21/02587 , H01L21/2251 , H01L21/306 , H01L21/31111 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66666 , H01L29/66833
摘要： A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path.
摘要翻译：为3D堆叠的非易失性存储器件提供制造工艺，其提供源极接触到堆叠底部的存储器孔。堆叠包括在衬底上的交替的控制栅极层和介电层，并且通过堆叠蚀刻存储器孔。该过程避免了在存储器孔的底部蚀刻通过膜的需要。相反，从存储孔的底部到堆叠的顶部形成路径。路径包括使用衬底电介质中的空隙沟槽的水平部分和在堆叠中蚀刻的通道。记忆膜，通道材料和电介质材料同时沉积在空隙和存储孔的整个内表面中。该路径被填充金属以形成连续的低电阻导电路径。

16. 发明申请

WO2015041824A3 THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHODS OF FABRICATION THEREOF 审中-公开
公开(公告)号：WO2015041824A3
公开(公告)日：2015-03-26
申请号：PCT/US2014/053055
申请日：2014-08-28
申请人： SANDISK TECHNOLOGIES, INC.
发明人： PACHAMUTHU, Jayavel , ALSMEIER, Johann , MAKALA, Raghuveer S. , LEE, Yao-Sheng
IPC分类号： H01L27/06 , H01L27/10 , H01L27/115
摘要： A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate, removing a portion of the first stack to form a first trench, filling the trench with a sacrificial material, forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material, removing a portion of the second stack to the sacrificial material to form a second trench, and removing the sacrificial material to form a continuous trench through the first stack and the second stack.

17. 发明申请

WO2015200021A1 THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE LINE AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有通道接触导通线的三维NAND器件及其制造方法
公开(公告)号：WO2015200021A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/035779
申请日：2015-06-15
申请人： SANDISK TECHNOLOGIES INC.
发明人： ZHANG, Yanli , SHOJI, Go , ALSMEIER, Johann , PACHAMUTHU, Jayavel , DONG, Yingda , YUAN, Jiahui
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7883
摘要： A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.
摘要翻译： NAND器件的NAND存储器单元区域包括基本上平行于衬底的主表面延伸的导电源线，基本上垂直于衬底的主表面延伸的第一半导体沟道，以及基本上延伸垂直于基片的主表面。第一半导体沟道的底部和侧部中的至少一个与导电源线接触，并且第二半导体沟道的底部和侧部中的至少一个与导电源线接触。

18. 发明申请

WO2015126664A1 A MULTILEVEL MEMORY STACK STRUCTURE AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：多个存储堆栈结构及其制造方法
公开(公告)号：WO2015126664A1
公开(公告)日：2015-08-27
申请号：PCT/US2015/015155
申请日：2015-02-10
申请人： SANDISK TECHNOLOGIES, INC.
发明人： PACHAMUTHU, Jayavel , ALSMEIER, Johann , CHIEN, Henry
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , H01L21/8221 , H01L27/0688 , H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L29/7926
摘要： A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.
摘要翻译：包括第一导电层和第一电绝缘层的交替层的第一叠层形成有第一台阶表面和其上的第一介电材料部分。可以通过第一台阶表面形成包括电介质金属氧化物的介质柱结构。可以形成下部存储器开口，并且填充有包括下部半导体沟道和掺杂半导体区域的一次性材料或下部存储器开口结构。可以顺序地形成至少一个介电材料层和包括第二导电层和第二电绝缘层的交替层的第二堆叠。上存储器开口可以通过第二堆叠和至少一个电介质材料层形成。可以在去除一次性材料之后形成记忆膜和半导体通道，或者可以在掺杂半导体区域上形成上半导体沟道。

19. 发明申请

WO2015038427A1 A SINGLE-SEMICONDUCTOR-LAYER CHANNEL IN A MEMORY OPENING FOR A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：用于三维非易失性存储器件的存储器中的单个半导体层通道
公开(公告)号：WO2015038427A1
公开(公告)日：2015-03-19
申请号：PCT/US2014/054246
申请日：2014-09-05
申请人： SANDISK TECHNOLOGIES, INC.
发明人： RABKIN, Peter , PACHAMUTHU, Jayavel , ALSMEIER, Johann
IPC分类号： H01L27/115
CPC分类号： H01L27/1157 , G11C16/0483 , H01L27/11524 , H01L27/11556 , H01L27/11578 , H01L27/11582
摘要： A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device.
摘要翻译：存储膜层通过第一材料层和第二材料层的交替堆叠形成在存储器开口中。牺牲材料层沉积在记忆膜层上。通过各向异性蚀刻去除存储器开口底部的牺牲材料层和存储膜层的水平部分，以暴露存储器开口下方的衬底，而牺牲材料层的垂直部分保护存储膜层的垂直部分。在去除对存储膜选择性的牺牲材料层之后，可以将掺杂的半导体材料层直接形成在存储器开口中的存储器开口和存储器膜上作为单个材料层，以形成存储器件的半导体通道。

20. 发明申请

WO2015038246A2 METHOD OF INTEGRATING SELECT GATE SOURCE AND MEMORY HOLE FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：为三维非易失性存储器件集成选择栅极源和存储器孔的方法
公开(公告)号：WO2015038246A2
公开(公告)日：2015-03-19
申请号：PCT/US2014/048160
申请日：2014-07-25
申请人： SANDISK TECHNOLOGIES, INC.
发明人： PACHAMUTHU, Jayavel , ALSMEIER, Johann , CHIEN, Henry
IPC分类号： H01L27/115
CPC分类号： H01L27/11551 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening.
摘要翻译：制造诸如三维NAND存储器串的半导体器件的方法包括在衬底的主表面上形成具有第一宽度的碳蚀刻停止层，在蚀刻停止层上形成交替材料层的叠层，将该堆叠蚀刻到蚀刻停止层以形成存储器开口，该存储器开口在存储器开口的底部具有小于蚀刻停止层的宽度的第二宽度，去除蚀刻停止层以提供具有较大宽度的空隙区域与存储器开口的第二宽度相比，在存储器开口的侧壁和空隙区域中形成记忆膜，并且在存储器开口中形成半导体沟道，使得存储膜位于半导体沟道和侧壁之间记忆开放。

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