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11. 发明申请

WO2006039177A1 FAULT PROCESSING FOR DIRECT MEMORY ACCESS ADDRESS TRANSLATION 审中-公开
标题翻译：直接存储访问地址转换的故障处理
公开(公告)号：WO2006039177A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/033933
申请日：2005-09-21
申请人： INTEL CORPORATION , MADUKKARUMUKUMANA, Rajesh , SCHOINAS, Ioannis , KING, Ku-Jei , VEMBU, Balaji , NEIGER, Gilbert , UHLIG, Richard
发明人： MADUKKARUMUKUMANA, Rajesh , SCHOINAS, Ioannis , KING, Ku-Jei , VEMBU, Balaji , NEIGER, Gilbert , UHLIG, Richard
IPC分类号： G06F11/07
CPC分类号： G06F11/0712 , G06F11/073 , G06F11/0745 , G06F11/0793 , G06F12/1081
摘要： An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.
摘要翻译：本发明的一个实施例是一种在直接存储器访问地址转换中处理故障的技术。寄存器组存储由I / O设备请求的输入/输出（I / O）事务产生的故障的故障处理的全局控制或状态信息。地址转换结构将访客物理地址转换为主机物理地址。访客物理地址对应于I / O事务，并映射到域。地址转换结构至少具有与域相关联的条目和用于故障处理的特定于域的控制信息。

12. 发明申请

WO2014084914A1 SECURE ENVIRONMENT FOR GRAPHICS PROCESSING UNITS 审中-公开
标题翻译：图形处理单元的安全环境
公开(公告)号：WO2014084914A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/048036
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： DEWAN, Prashant , SAVAGAONKAR, Uday R. , DURHAM, David M. , SCHMITZ, Paul S. , MARTIN, Jason , GOLDSMITH, Michael A. , SAHITA, Ravi , MCKEEN, Francis X. , ROZAS, Carlos V. , VEMBU, Balaji , SCOTT, Janus , STRONGIN, Geoffrey S. , KANG, Xiaozhu , GREWAL, Karanvir S. , CHHABRA, Siddhartha , TRIVEDI, Alpa T. Narendra
IPC分类号： G06F21/50
CPC分类号： G06F21/64 , G06F21/53 , G06F21/56
摘要： In accordance with some embodiments, a protected execution environment may be defined for a graphics processing unit. This framework not only protects the workloads from malware running on the graphics processing unit but also protects those workloads from malware running on the central processing unit. In addition, the trust framework may facilitate proof of secure execution by measuring the code and data structures used to execute the workload. If a part of the trusted computing base of this framework or protected execution environment is compromised, that part can be patched remotely and the patching can be proven remotely throughout attestation in some embodiments.
摘要翻译：根据一些实施例，可以为图形处理单元定义受保护的执行环境。该框架不仅保护了图形处理单元上运行的恶意软件的工作负载，还保护了这些工作负载免受中央处理单元上运行的恶意软件。此外，信任框架可以通过测量用于执行工作负载的代码和数据结构来促进安全执行的证明。如果该框架或受保护的执行环境的可信计算基础的一部分受到损害，那么该部分可以被远程修补，并且在一些实施例中可以通过证明来远程验证修补。

13. 发明申请

WO2018009277A1 GRAPHICS COMMAND PARSING MECHANISM 审中-公开
标题翻译：图形命令分解机制
公开(公告)号：WO2018009277A1
公开(公告)日：2018-01-11
申请号：PCT/US2017/033381
申请日：2017-05-18
申请人： INTEL CORPORATION
发明人： BOLES, Jeffery S. , NALLURI, Hema C. , VEMBU, Balaji , SHAH, Pritav H. , APODACA, Michael , RAMADOSS, Murali , SAPTARSHI, Lalit K.
IPC分类号： G06F9/30 , G06F12/0831
CPC分类号： G06T1/60 , G06T1/20
摘要： A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.
摘要翻译：描述命令流处理的机制。如在此描述的，实施例的方法包括从存储器获取高速缓存行以先进先出缓冲器（FIFO）填充命令，其中所获取的高速缓存行处理命令所需的过量数据，第一解析器获取并执行批次存储在命令FIFO中的命令和第二解析器来获取命令并执行存储在命令FIFO中的批处理命令和非批处理命令。

14. 发明申请

WO2017200660A1 COMMAND PROCESSING FOR GRAPHICS TILE-BASED RENDERING 审中-公开
标题翻译：指令处理的图形基于TILE的渲染
公开(公告)号：WO2017200660A1
公开(公告)日：2017-11-23
申请号：PCT/US2017/026764
申请日：2017-04-10
申请人： INTEL CORPORATION
发明人： VEMBU, Balaji , DOYLE, Peter L. , APODACA, Michael , NALLURI, Hema C. , BOLES, Jeffery S.
IPC分类号： G06T15/80 , G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06T1/60 , G06T11/40 , G06T15/005 , G06T15/40 , G06T15/80
摘要： The same set of render commands can be re-executed for each of a plurality of tiles making up a graphic scene to be rendered. Each time the list of commands is executed, the way the commands are executed may be modified based on information received from tile pre-processing. Specifically, a jump if command may be inserted into the command list. When this command is encountered, a determination is made, based on information received from tile pre-processing pipeline, whether to execute the command for the next primitive or not. If the next primitive is to be culled then the command for the next primitive is not executed and the flow moves past that command. If the next primitive is to be executed then the jump is not implemented. This enables avoiding reloading the same list of commands over and over for every tile.
摘要翻译：对于构成要呈现的图形场景的多个拼贴块中的每个拼贴块，可以重新执行相同的一组渲染命令。每次执行命令列表时，可以基于从瓦片预处理接收到的信息来修改命令的执行方式。具体而言，可以将跳转if命令插入到命令列表中。当遇到这个命令时，基于从瓦片预处理管线接收到的信息确定是否执行下一个原语的命令。如果要剔除下一个基元，则不执行下一个基元的命令，并且流程移过该命令。如果要执行下一个基元，则跳转不执行。这样可以避免为每个tile重复加载相同的命令列表。

15. 发明申请

WO2017052949A1 POSITION ONLY SHADER CONTEXT SUBMISSION THROUGH A RENDER COMMAND STREAMER 审中-公开
标题翻译：位置只能通过渲染命令流程表上传提交上传
公开(公告)号：WO2017052949A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/048524
申请日：2016-08-25
申请人： INTEL CORPORATION
发明人： RAMADOSS, Murali , VEMBU, Balaji , NALLURI, Hema C. , APODACA, Michael , BOLES, Jeffery S.
IPC分类号： G06T1/20 , G06T1/60 , G06T15/08 , G06T17/10
CPC分类号： G06T15/80 , G06F9/48 , G06T1/20
摘要： By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments. Software separates command sequences for each pipe to enable the POSH pipe to run ahead of a Render pipe. Infrastructre is provided to synchronize the two pipes through software inserted commands. A Render plus POSH pipeline may be a single monolithic engine without changes to a software scheduler, removing the complexity and the latencies involved in scheduling.
摘要翻译：通过调度/管理到POSH管道的工作负载，可以在一些实施例中利用对软件调度器的最小影响的并行性。软件分离每个管道的命令序列，以使POSH管道能够在渲染管道之前运行。提供了基础设施，通过软件插入的命令来同步两个管道。渲染加POSH管道可以是单个单片引擎，而不改变软件调度器，消除了调度中涉及的复杂性和延迟。

16. 发明申请

WO2016167876A1 SUPPORTING MULTI-LEVEL NESTING OF COMMAND BUFFERS IN GRAPHICS COMMAND STREAMS AT COMPUTING DEVICES 审中-公开
标题翻译：在计算机设备的图形命令流中支持多层次的命令缓存
公开(公告)号：WO2016167876A1
公开(公告)日：2016-10-20
申请号：PCT/US2016/018490
申请日：2016-02-18
申请人： INTEL CORPORATION
发明人： NALLURI, Hema Chand , VEMBU, Balaji , BOLES, Jeffery S.
IPC分类号： G06T1/20 , G06F9/30 , G06T1/60
CPC分类号： G06T1/20 , G06F12/00 , G06F12/0811 , G06F12/0875 , G06F2212/1016 , G06F2212/455 , G06T1/60
摘要： A mechanism is described for facilitating multi-level nesting of batch buffers at computing devices. A method of embodiments, as described herein, includes facilitating a hardware extension to accommodate a plurality of batch buffers to engage in a multi-level nesting, where the plurality of batch buffers are associated with a graphics processor of a computing device. The method may further include facilitating the multi-level nesting of the plurality of batch buffers, where the multi-level nesting is spread over a plurality of levels associated with the plurality of batch buffers, where the plurality of levels include more than two levels of nesting associated with more than two batch buffers of the plurality of batch buffers.
摘要翻译：描述了一种机制，用于促进计算设备上批量缓冲区的多级嵌套。如本文所述的实施例的方法包括促进硬件扩展以容纳多个批次缓冲器以参与多级嵌套，其中多个批处理缓冲器与计算设备的图形处理器相关联。该方法还可以包括促进多级批量缓冲器的多级嵌套，其中多级嵌套分布在与多个批量缓冲器相关联的多个级别上，其中多个级别包括多于两级的与多个批次缓冲器中的两个以上批处理缓冲器相关联的嵌套。

17. 发明申请

WO2015048069A1 SECURE VIDEO OUPUT PATH 审中-公开
标题翻译：安全视频OUPUT路径
公开(公告)号：WO2015048069A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/057121
申请日：2014-09-24
申请人： INTEL CORPORATION
发明人： CHHABRA, Siddhartha , SAVAGAONKAR, Uday R. , DEWAN, Prashant , DURHAM, David M. , VEMBU, Balaji , KANG, Xiaozhu , JANUS, Scott , MARTIN, Jason , SCARLATA, Vincent R.
IPC分类号： G06F21/60
CPC分类号： G06F21/82 , G06F21/84 , G06F21/85 , H04N21/4122 , H04N21/4143 , H04N21/4367
摘要： Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a processing core communicatively coupled to the architecturally protected memory, the processing core comprising a processing logic configured to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory; wherein the processing logic is further configured to provide a secure video output path by generating an output surface bitmap encrypted with a first encryption key and storing an encrypted first encryption key in an external memory, wherein the encrypted first encryption key is produced by encrypting the first encryption key with a second encryption key.
摘要翻译：用于将输出表面位图安全传送到显示引擎的系统和方法。一个示例处理系统包括：架构受保护的存储器; 以及处理核心，其通信地耦合到所述架构保护的存储器，所述处理核心包括处理逻辑，所述处理逻辑被配置为通过执行以下中的至少一个来实现架构保护的执行环境：执行驻留在所述架构受保护的存储器中的指令，建筑保护记忆; 其中所述处理逻辑还被配置为通过生成用第一加密密钥加密并将加密的第一加密密钥存储在外部存储器中的输出表面位图来提供安全视频输出路径，其中所述加密的第一加密密钥是通过加密所述第一加密密钥具有第二加密密钥的加密密钥。

18. 发明申请

WO2014099035A1 OFFLOADING TOUCH PROCESSING TO A GRAPHICS PROCESSOR 审中-公开
标题翻译：卸载触摸处理到图形处理器
公开(公告)号：WO2014099035A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/048795
申请日：2013-06-29
申请人： INTEL CORPORATION
发明人： VEMBU, Balaji , POISNER, David I. , KUMAR, Arvind , GANDRA, Chaitanya R.
IPC分类号： G06F13/10 , G06F13/14 , G06F13/16
CPC分类号： G06T1/20
摘要： In an embodiment, a processor includes a graphics domain including a graphics engines each having at least one execution unit. The graphics domain is to schedule a touch application offloaded from a core domain to at least one of the plurality of graphics engines. The touch application is to execute responsive to an update to a doorbell location in a system memory coupled to the processor, where the doorbell location is written responsive to a user input to the touch input device. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括包括图形引擎的图形域，每个图形引擎具有至少一个执行单元。图形域是将从核心域卸载的触摸应用计划到多个图形引擎中的至少一个。所述触摸应用是响应于与耦合到所述处理器的系统存储器中的门铃位置的更新来执行的，其中响应于对所述触摸输入设备的用户输入写入所述门铃位置。描述和要求保护其他实施例。

19. 发明申请

WO2018063554A1 THREAD PRIORITY MECHANISM 审中-公开
标题翻译：线程优先机制
公开(公告)号：WO2018063554A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/047191
申请日：2017-08-16
申请人： INTEL CORPORATION
发明人： KOKER, Altug , SURTI, Prassonkumar , LUEH, Guei-Yuan , MAIYURAN, Subramaniam , AKENINE-MOLLER, Tomas , COWPERTHWAITE, David J. , VEMBU, Balaji
IPC分类号： G06F9/48 , G06F9/50 , G06F13/16 , G06T1/20 , G06T15/80
CPC分类号： G06F9/4831 , G06F9/4881
摘要： A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a thread dispatcher to assign a priority class to each of a plurality of processing threads prior to dispatching the one or more processing threads, a plurality of execution units to process the threads, a shared resource coupled to each of the plurality of execution units and an arbitration unit to grant access to the shared resource to a first of the plurality of execution units based on the priority class of a thread being executed at the first execution unit.
摘要翻译：描述处理设备。该装置包括图形处理单元（GPU），该图形处理单元包括线程调度器，用于在分派一个或多个处理线程之前向多个处理线程中的每一个分配优先级类，用于处理线程的多个执行单元，资源，其耦合到所述多个执行单元中的每一个执行单元以及仲裁单元，以基于在所述第一执行单元处执行的线程的优先级等级，将对所述共享资源的访问许可给所述多个执行单元中的第一执行单元。

20. 发明申请

WO2017155610A1 METHOD AND APPARATUS FOR EFFICIENT SUBMISSION OF WORKLOAD TO A HIGH PERFORMANCE GRAPHICS SUB-SYSTEM 审中-公开
标题翻译：将工作负荷有效提交给高性能图形子系统的方法和设备
公开(公告)号：WO2017155610A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/013795
申请日：2017-01-17
申请人： INTEL CORPORATION
发明人： VEMBU, Balaji , BALA, Kritika , RAMADOSS, Murali , NALLURI, Hema , BOLES, Jeffery , FRIZZELL, Jeffrey , KOSTON, Joseph
IPC分类号： G06F9/38 , G06T1/20
摘要： Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.
摘要翻译：实施例提供了一种装置，该装置包括图形处理子系统，该图形处理子系统包括一个或多个图形引擎和图形调度器，以调度多个工作项的提交队列以在图形处理的一个或多个图形引擎上执行子系统。图形调度器可以被配置为通过写入映射到图形处理子系统内的逻辑的存储器映射地址来构建提交队列，并且在构建提交队列之后显式地将提交队列提交给图形引擎。 p>

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