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11. 发明申请

WO2005076816A3 APPARATUS AND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONAL DATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM 审中-公开
公开(公告)号：WO2005076816A3
公开(公告)日：2005-08-25
申请号：PCT/US2005/002410
申请日：2005-01-25
申请人： MICRON TECHNOLOGY, INC. , LARSON, Douglas, A. , CRONIN, Jeffrey, J.
发明人： LARSON, Douglas, A. , CRONIN, Jeffrey, J.
IPC分类号： G06F12/00
摘要： A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

12. 发明申请

WO2005076816A2 APPARATUS AND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONAL DATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM 审中-公开
标题翻译：基于HUB的存储器子系统中的双向数据总线的数据旁路的装置和方法
公开(公告)号：WO2005076816A2
公开(公告)日：2005-08-25
申请号：PCT/US2005002410
申请日：2005-01-25
申请人： MICRON TECHNOLOGY INC , LARSON DOUGLAS A , CRONIN JEFFREY J
发明人： LARSON DOUGLAS A , CRONIN JEFFREY J
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/28 , G06F12/0888 , G06F13/161
摘要： A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
摘要翻译：存储器集线器包括用于耦合到相应的数据总线的第一和第二链路接口，耦合到第一和第二链路接口的数据路径，以及数据在第一和第二链路接口之间传送的数据路径，并且还包括写入旁路电路，将数据路径耦合到数据路径上的数据路径，并临时存储写入数据，以允许在暂时存储写入数据时通过数据路径传送读取数据。提供了一种将数据写入存储器系统中的存储器位置的方法，其包括访问存储器系统中的读取数据，向存储器系统提供写入数据，以及将写入数据耦合到寄存器以进行临时存储。在提供读取的数据之后，将写入数据重新耦合到存储器总线并写入存储器位置。

13. 发明申请

WO2012166531A3 APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS 审中-公开
标题翻译：装置包括记忆系统控制器及相关方法
公开(公告)号：WO2012166531A3
公开(公告)日：2013-03-28
申请号：PCT/US2012039390
申请日：2012-05-24
申请人： MICRON TECHNOLOGY INC , LARSON DOUGLAS A , JEDDELOH JOSEPH M
发明人： LARSON DOUGLAS A , JEDDELOH JOSEPH M
IPC分类号： G11C7/10 , G06F12/00 , G11C16/06
CPC分类号： G06F5/14 , G06F12/023 , G06F12/0246 , G06F13/28 , G06F2205/126 , G06F2212/7201 , G11C7/10 , G11C16/06 , H04L49/901
摘要： Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.
摘要翻译：存储器系统控制器可以包括硬件主器件，第一缓冲器和耦合到硬件主器件和第一缓冲器的开关。交换机可以包括第二缓冲器和缓冲器分配管理（BAM）电路。 BAM电路可以包括缓冲标签池。缓冲标签池可以包括标签，每个标签标识相应的第一缓冲器或相应的第二缓冲器。 BAM电路可以被配置为响应于来自硬件主机的分配请求而向硬件主机分配标签。可以将BAM电路配置为优先于识别标识第一缓冲器的标签上识别第二缓冲器的标签的分配。

14. 发明申请

WO2012166522A3 APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS 审中-公开
公开(公告)号：WO2012166522A3
公开(公告)日：2012-12-06
申请号：PCT/US2012/039364
申请日：2012-05-24
申请人： MICRON TECHNOLOGY, INC. , LARSON, Douglas, A. , BROWN, Jeffrey, R.
发明人： LARSON, Douglas, A. , BROWN, Jeffrey, R.
IPC分类号： G11C16/06 , G06F12/00
摘要： Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units.

15. 发明申请

WO2005119457A3 METHOD AND SYSTEM FOR TERMINATING WRITE COMMANDS IN A HUB-BASED MEMORY SYSTEM 审中-公开
标题翻译：基于HUB的存储系统终止写命令的方法和系统
公开(公告)号：WO2005119457A3
公开(公告)日：2007-06-21
申请号：PCT/US2005018783
申请日：2005-05-27
申请人： MICRON TECHNOLOGY INC , CRONIN JEFFREY J , LARSON DOUGLAS A
发明人： CRONIN JEFFREY J , LARSON DOUGLAS A
IPC分类号： G06F12/00 , G06F13/42
CPC分类号： G06F13/423 , G06F13/1684 , G06F13/4256
摘要： A memory hub (140) receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub (140). The memory hub (140) operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices (130). The memory hub (140) operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub (140).
摘要翻译：存储器集线器（140）接收下游存储器命令并处理每个接收到的下游存储器命令以确定存储器命令是否包括指向存储器集线器（140）的写入命令。当写入命令被引导到集线器以开发适于被应用于存储器件的存储器访问信号时，存储器集线器（140）以第一模式工作（130）。当写入命令不指向集线器以在适于耦合到下游存储器集线器（140）的下游输出端口上提供命令的写入数据时，存储器集线器（140）以第二模式操作。

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