专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

WO2013026038A1 JOINT LINEAR AND NON-LINEAR CANCELLATION OF TRANSMIT SELF-JAMMING INTERFERENCE 审中-公开
标题翻译：接头线性和非线性消除传输自我干扰
公开(公告)号：WO2013026038A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/051476
申请日：2012-08-17
申请人： QUALCOMM INCORPORATED , RIMINI, Roberto , HEIDMANN, Peter D. , GUDEM, Prasad S. , VERMA, Sumit , BURKE, Joseph
发明人： RIMINI, Roberto , HEIDMANN, Peter D. , GUDEM, Prasad S. , VERMA, Sumit , BURKE, Joseph
IPC分类号： H04B1/10 , H04B1/30 , H04B1/52
CPC分类号： H04B1/109 , H04B1/30 , H04B1/525
摘要： Certain aspects of the present disclosure propose an adaptive joint linear and non-linear digital filter that can adaptively estimate and reconstruct cascaded effects of linear and non-linear self-jamming distortions introduced by non-linearities in the transmit and/or receive chains. The proposed digital filter may be used to cancel second-order inter-modulation distortion (IM2) generated in the receive chain and/or harmonic distortion generated in the transmit chain, as well as other distortions introduced by the transmit/and or receive chains.
摘要翻译：本公开的某些方面提出了一种自适应联合线性和非线性数字滤波器，其可以自适应地估计和重建由发送和/或接收链中的非线性引入的线性和非线性自干扰失真的级联效应。所提出的数字滤波器可以用于消除在接收链中产生的二阶互调失真（IM2）和/或在发送链中产生的谐波失真以及由发送/和/或接收链引入的其他失真。

12. 发明申请

WO2010025288A1 INTERFERENCE DETECTION APPARATUS AND METHOD 审中-公开
标题翻译：干扰检测装置和方法
公开(公告)号：WO2010025288A1
公开(公告)日：2010-03-04
申请号：PCT/US2009/055240
申请日：2009-08-27
申请人： QUALCOMM Incorporated , PATEL, Shrenik , GUDEM, Prasad, S. , PALAKURTY, Saraswathi
发明人： PATEL, Shrenik , GUDEM, Prasad, S. , PALAKURTY, Saraswathi
IPC分类号： H04B1/10
CPC分类号： H04K3/82 , H04B1/1027 , H04B1/109
摘要： Techniques for detecting jammers in a received signal are described. A jammer detector includes a jammer filter for attenuating transmit signals leaked into the receive path, a pulse generator for converting the interference signals into discrete-level pulses, and a pulse processor for determining the presence of jammers in the discrete-level pulses. In an exemplary embodiment, the pulse processor is configured to further discriminate among close-in jammers that are close to the desired receive frequency, far-away jammers, and jammers arising from the transmit signals leaked into the receive path. In another exemplary embodiment, hysteresis is provided in the pulse generator to enable the generation of reliable pulses. Further aspects include configuring the jammer detector for operation in a plurality of frequency bands and/or according to a plurality of communications standards.
摘要翻译：描述用于检测接收信号中的干扰的技术。干扰检测器包括用于衰减泄漏到接收路径中的发射信号的干扰滤波器，用于将干扰信号转换成离散电平脉冲的脉冲发生器，以及用于确定离散电平脉冲中干扰的存在的脉冲处理器。在示例性实施例中，脉冲处理器被配置为进一步区分接近期望接收频率的接近干扰信号，远距离干扰信号和从泄漏到接收路径中的发射信号产生的干扰。在另一个示例性实施例中，在脉冲发生器中提供迟滞以使能产生可靠的脉冲。另外的方面包括将干扰检测器配置为在多个频带中操作和/或根据多个通信标准。

13. 发明申请

WO2010022093A1 HIGH-LINEARITY LOW-NOISE RECEIVER WITH LOAD SWITCHING 审中-公开
标题翻译：具有负载开关的高线性低噪声接收器
公开(公告)号：WO2010022093A1
公开(公告)日：2010-02-25
申请号：PCT/US2009/054214
申请日：2009-08-18
申请人： QUALCOMM INCORPORATED , LIU, Li , GUDEM, Prasad, S.
发明人： LIU, Li , GUDEM, Prasad, S.
IPC分类号： H03F1/56 , H03F3/45
CPC分类号： H03F1/32 , H03F1/0277 , H03F1/223 , H03F1/56 , H03F3/45188 , H03F3/72 , H03F2200/294 , H03F2200/336 , H03F2203/45386 , H03F2203/45394 , H03F2203/45726 , H03F2203/7206 , H03F2203/7236 , H04B1/109 , H04B1/18
摘要： A receiver includes a low noise amplifier (LNA) and multiple pairs of mixers. The LNA receives and amplifies an LNA input signal and provides at least one LNA output signal. Each pair of mixers downconverts one of the at least one LNA output signal when enabled. Each pair of mixers may be selectively enabled or disabled, e.g., based on a mode selected from among multiple modes. In one design, the LNA includes multiple load sections coupled in parallel. Each load section may be selectively enabled or disabled, e.g., based on the selected mode. In one design, first and second pairs of mixers and first and second load sections may be enabled for a high linearity mode. The first pair of mixers and the first load section may be enabled and the second pair of mixers and the second load section may be disabled for a low linearity mode.
摘要翻译：接收机包括低噪声放大器（LNA）和多对混频器。 LNA接收并放大LNA输入信号并提供至少一个LNA输出信号。当使能时，每对混频器降低至少一个LNA输出信号之一。可以例如基于从多个模式中选择的模式来选择性地启用或禁用每对混频器。在一种设计中，LNA包括并联耦合的多个负载部分。可以例如基于所选择的模式来选择性地启用或禁用每个加载部分。在一种设计中，第一和第二对混频器以及第一和第二负载部分可以被启用用于高线性模式。可以启用第一对混频器和第一负载部分，并且可以对低线性模式禁用第二对混频器和第二负载部分。

14. 发明申请

WO2009149082A2 METHODS AND APPARATUS FOR POWER REDUCTION IN A TRANSCEIVER 审中-公开
标题翻译：收发机功率降低的方法和装置
公开(公告)号：WO2009149082A2
公开(公告)日：2009-12-10
申请号：PCT/US2009045971
申请日：2009-06-02
申请人： QUALCOMM INC , GUDEM PRASAD S , CICCARELLI STEVEN C , MOK KEN TSZ KIN , KWOK SAI C
发明人： GUDEM PRASAD S , CICCARELLI STEVEN C , MOK KEN TSZ KIN , KWOK SAI C
IPC分类号： G05F1/56 , H04B1/16
CPC分类号： H03F1/304 , H03F1/0244 , H03F1/32 , H03F3/195 , H03F3/24 , H03F2200/451 , H03F2200/468 , H03F2200/511
摘要： An integrated circuit for achieving power reduction in a transceiver may include a jammer detector that determines an interference level corresponding to a received signal, and a transmit power detector that determines a required transmit power level for a transmitted signal. The integrated circuit may also include at least one of the following: a process monitor that determines process corners of components within the receiver and/or the transmitter, and a temperature monitor that determines a temperature of the receiver and/or the transmitter. The integrated circuit may also include a state machine. The state machine may transition the receiver from a high linearity mode to a low linearity mode if a set of operating conditions is satisfied. Similarly, the state machine may transition the transmitter from a high power mode to a low power mode if a set of operating conditions is satisfied.
摘要翻译：用于实现收发机功率降低的集成电路可以包括干扰检测器，其确定与接收信号相对应的干扰电平;以及发射功率检测器，其确定发射信号的所需发射功率电平。集成电路还可以包括以下中的至少一个：确定接收器和/或发射器内的部件的过程角的过程监视器以及确定接收器和/或发射器的温度的温度监视器。集成电路还可以包括状态机。如果满足一组操作条件，状态机可以将接收器从高线性模式转换到低线性模式。类似地，如果满足一组操作条件，则状态机可以将发射机从高功率模式转换到低功率模式。

15. 发明申请

WO2009114638A1 HIGH-LINEARITY RECEIVER WITH TRANSMIT LEAKAGE CANCELLATION 审中-公开
标题翻译：具有发送泄漏消除功能的高线性接收器
公开(公告)号：WO2009114638A1
公开(公告)日：2009-09-17
申请号：PCT/US2009/036849
申请日：2009-03-11
申请人： QUALCOMM INCORPORATED , GUDEM, Prasad, S. , CHANG, Li-Chung
发明人： GUDEM, Prasad, S. , CHANG, Li-Chung
IPC分类号： H04B1/52
CPC分类号： H04B1/525
摘要： Techniques for performing transmit (TX) leakage cancellation are described. A receiver includes a low noise amplifier (LNA) and a TX leakage canceller. The LNA amplifies a receiver input signal and provides an amplified signal. The TX leakage canceller includes a downconverter, a notch filter, and an upconverter. The downconverter downconverts a canceller input signal (e.g., obtained from the LNA output) with a first LO signal at a transmit frequency and provides a downconverted signal. The notch filter filters the downconverted signal to pass an undesired signal (e.g., a TX leakage signal) and attenuate a jammer and a desired signal in the canceller input signal. The upconverter upconverts the filtered signal with a second LO signal at the transmit frequency and provides a feedback signal. The feedback signal is subtracted at the input or output of the LNA to cancel the undesired signal.
摘要翻译：描述用于执行发射（TX）泄漏消除的技术。接收机包括低噪声放大器（LNA）和TX泄漏消除器。 LNA放大接收机输入信号并提供放大信号。 TX泄漏消除器包括下变频器，陷波滤波器和上变频器。下变频器以发射频率以第一LO信号下变频消除器输入信号（例如，从LNA输出获得），并提供下变频信号。陷波滤波器对下变频信号进行滤波以传递不期望的信号（例如，TX泄漏信号），并且在消除器输入信号中衰减干扰信号和期望信号。上变频器以滤波信号以发射频率的第二LO信号上变频，并提供反馈信号。在LNA的输入或输出处减去反馈信号以消除不需要的信号。

16. 发明申请

WO2009108815A1 DELTA-SIGMA MODULATOR CLOCK DITHERING IN A FRACTIONAL-N PHASE-LOCKED LOOP 审中-公开
标题翻译： DELTA-SIGMA调制器时钟在一个分段N相锁定环路
公开(公告)号：WO2009108815A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/035349
申请日：2009-02-26
申请人： QUALCOMM Incorporated , XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
发明人： XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
IPC分类号： H03L7/197
CPC分类号： H03L7/1974
摘要： The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.
摘要翻译：在分数N锁相环中提供给Δ-Σ调制器的时钟信号被抖动。在一个示例中，PLL包括新颖的可编程时钟抖动电路。可编程时钟抖动电路可通过串行总线进行控制，以选择的几种方式对时钟信号的相位进行抖动。如果时钟信号以第一种方式抖动（伪随机相位抖动），则由Δ-Σ调制器产生的数字噪声的功率在频带上扩展，从而降低噪声干扰其他电路的程度。如果时钟信号以第二种方式抖动（旋转相位抖动），则数字噪声的功率被频移，使得噪声干扰另一电路的程度降低。可编程时钟抖动电路可以以其他方式进行控制。例如，抖动可以可编程地禁用。

17. 发明申请

WO2009097353A1 METHOD AND APPARATUS FOR REDUCING INTERMODULATION DISTORTION IN AN ELECTRONIC DEVICE HAVING AN AMPLIFIER CIRCUIT 审中-公开
标题翻译：用于减小具有放大器电路的电子设备中的互调失真的方法和装置
公开(公告)号：WO2009097353A1
公开(公告)日：2009-08-06
申请号：PCT/US2009/032272
申请日：2009-01-28
申请人： QUALCOMM INCORPORATED , DENG, Junxiong , LIU, Li , GUDEM, Prasad, S.
发明人： DENG, Junxiong , LIU, Li , GUDEM, Prasad, S.
IPC分类号： H03F3/193 , H03F1/32 , H03F1/34
CPC分类号： H03F3/193 , H03F1/223 , H03F1/3205 , H03F1/34 , H03F2200/294 , H03F2201/3206
摘要： An electronic device includes an amplifier circuit coupled to a linearizer. The amplifier circuit may receive a first input signal including first and second frequencies and generate a first output signal including a delta frequency signal at a delta frequency, which is the difference between the first frequency and the second frequency. The linearizer includes a signal detector circuit, a current-mirror circuit, a low pass filter, a phase shifter, and a bias circuit. The signal detector circuit may generate a second output signal. The current-mirror circuit may adjust an amplitude of a signal. The low pass filter may eliminate a portion of the second output signal having frequencies greater than the delta frequency. The phase shifter may generate a feedback signal corresponding to the delta frequency signal. An amplitude and/or a phase of the feedback signal is different from an amplitude and/or a phase of the delta frequency signal.
摘要翻译：电子设备包括耦合到线性化器的放大器电路。放大器电路可以接收包括第一和第二频率的第一输入信号，并产生第一输出信号，该第一输出信号包括第一频率和第二频率之间的差异的增量频率的增量频率信号。线性化器包括信号检测器电路，电流镜电路，低通滤波器，移相器和偏置电路。信号检测器电路可以产生第二输出信号。电流镜电路可以调节信号的幅度。低通滤波器可以消除具有大于Δ频率的频率的第二输出信号的一部分。移相器可以产生对应于Δ频率信号的反馈信号。反馈信号的振幅和/或相位与增量频率信号的振幅和/或相位不同。

18. 发明申请

WO2009026413A1 ACTIVE CIRCUITS WITH LOAD LINEARIZATION 审中-公开
标题翻译：具有负载线性化的有源电路
公开(公告)号：WO2009026413A1
公开(公告)日：2009-02-26
申请号：PCT/US2008/073812
申请日：2008-08-21
申请人： QUALCOMM Incorporated , LIU, Li , GUDEM, Prasad S.
发明人： LIU, Li , GUDEM, Prasad S.
IPC分类号： H03F1/26 , H03F1/32 , H04B1/10 , H04B1/52
CPC分类号： H04B1/109 , H03F1/223 , H03F1/3205 , H03F1/3211 , H03F3/45179 , H03F3/45188 , H03F2200/453 , H03F2203/45306 , H03F2203/45352 , H03F2203/45386 , H03F2203/45394 , H04B1/525
摘要： Active circuits with active loads linearized via distortion cancellation are described. In one design, an apparatus includes a first stage and a load stage. For an amplifier, the first stage amplifies an input signal and provides an output signal having a larger signal level. For a mixer, the first stage mixes an input signal with an LO signal and provides an output signal. The load stage provides an active load for the first stage and is linearized by canceling distortion generated by the active load. In one design, the load stage includes a first transistor that provides the active load and generates distortion due to its nonlinearity. The load stage further includes at least one transistor that generates a replica of the distortion from the first transistor. The distortion replica is used to cancel the distortion from the first transistor. The first stage may also be linearized with distortion cancellation.
摘要翻译：描述了通过失真消除线性化的有源负载的有源电路。在一种设计中，装置包括第一级和负载级。对于放大器，第一级放大输入信号并提供具有较大信号电平的输出信号。对于混频器，第一级将输入信号与LO信号混频并提供输出信号。负载级为第一级提供有效负载，并通过消除由有效负载产生的失真来线性化。在一种设计中，负载级包括提供有源负载并由于其非线性而产生失真的第一晶体管。负载级还包括至少一个晶体管，其产生来自第一晶体管的失真的复制品。失真复制品用于消除第一晶体管的失真。第一级也可以通过失真消除线性化。

19. 发明申请

WO2011153077A1 REDUCING POWER CONSUMPTION BY IN-CIRCUIT MEASUREMENT OF RECEIVE BAND ATTENUATION AND/OR NOISE 审中-公开
标题翻译：通过线路衰减测量和/或噪声降低功耗
公开(公告)号：WO2011153077A1
公开(公告)日：2011-12-08
申请号：PCT/US2011/038245
申请日：2011-05-26
申请人： QUALCOMM Incorporated , GUDEM, Prasad S. , ASURI, Bhushan , LAU, Soon-Seng , LEUNG, Wingching Vincent
发明人： GUDEM, Prasad S. , ASURI, Bhushan , LAU, Soon-Seng , LEUNG, Wingching Vincent
IPC分类号： H04B1/10 , H04B1/52 , H04W52/02
CPC分类号： H04B1/1027 , H03F1/02 , H03F3/24 , H04B1/525 , H04B2001/045 , H04W52/0245 , Y02D70/1242 , Y02D70/164 , Y02D70/40
摘要： Although the duplexer in a full-duplex transceiver circuit may only be guaranteed by the duplexer manufacturer to have a transmit band rejection from its TX port to its RX port of a certain amount, and may only be guaranteed to have a receive band rejection of another amount, the actual transmit band rejection and the actual receive band rejection of a particular instance of the duplexer may be better than specified. Rather than consuming excess power in the receiver and/or transmitter in order to meet performance requirements assuming the duplexer only performs as well as specified, the duplexer's in-circuit performance is measured as part of a transmitter-to-receiver isolation determination. Transmitter and/or receiver power settings are reduced where possible to take advantage of the measured better-than-specified in-circuit duplexer performance, while still meeting transceiver performance requirements. Power settings are not changed during normal transmit and receive mode operation.
摘要翻译：虽然全双工收发器电路中的双工器可能只能由双工器制造商保证从其TX端口到其一定数量的RX端口的发射波段抑制，并且只能保证具有另一个的接收频带抑制数量，双工器的特定实例的实际发射频带抑制和实际接收频带抑制可能优于指定的。假设双工器仅执行指定，而不是在接收机和/或发射机中消耗多余的功率，以满足性能要求，则双工器的在线性能是作为发射机到接收机隔离确定的一部分进行测量的。发射机和/或接收机功率设置在可能的情况下可以减少，以便在仍然满足收发器性能要求的同时利用测得的优于指定的在线双工器性能。在正常的发送和接收模式操作期间，电源设置不会改变。

20. 发明申请

WO2011153076A2 REDUCING POWER CONSUMPTION BY TAKING ADVANTAGE OF SUPERIOR IN-CIRCUIT DUPLEXER PERFORMANCE 审中-公开
标题翻译：通过获得超级电路双工器性能优势降低功耗
公开(公告)号：WO2011153076A2
公开(公告)日：2011-12-08
申请号：PCT/US2011/038241
申请日：2011-05-26
申请人： QUALCOMM INCORPORATED , GUDEM, Prasad S. , LAU, Soon-Seng , LIU, Li
发明人： GUDEM, Prasad S. , LAU, Soon-Seng , LIU, Li
IPC分类号： H04B1/10 , H04B1/16 , H04B1/52
CPC分类号： H04B1/525 , H04B1/109 , H04W52/0238 , Y02D70/1242 , Y02D70/164 , Y02D70/40
摘要： Although the duplexer in a full-duplex transceiver circuit may only be guaranteed by the duplexer manufacturer to have a transmit band rejection from its TX port to its RX port of a certain amount, and may only be guaranteed to have a receive band rejection of another amount, the actual transmit band rejection and the actual receive band rejection of a particular instance of the duplexer may be better than specified. Rather than consuming excess power in the receiver and/or transmitter in order to meet performance requirements assuming the duplexer only performs as well as specified, the duplexer's in-circuit performance is measured as part of a transmitter-to-receiver isolation determination. Transmitter and/or receiver power settings are reduced where possible to take advantage of the measured better-than-specified in-circuit duplexer performance, while still meeting transceiver performance requirements. Power settings are not changed during normal transmit and receive mode operation.
摘要翻译：虽然全双工收发器电路中的双工器可能只能由双工器制造商保证从其TX端口到其一定数量的RX端口的发射波段抑制，并且只能保证具有另一个的接收频带抑制数量，双工器的特定实例的实际发射频带抑制和实际接收频带抑制可能优于指定的。假设双工器仅执行指定，而不是在接收机和/或发射机中消耗多余的功率，以满足性能要求，则双工器的在线性能是作为发射机到接收机隔离确定的一部分进行测量的。发射机和/或接收机功率设置在可能的情况下可以减少，以便在仍然满足收发器性能要求的同时利用测得的优于指定的在线双工器性能。在正常的发送和接收模式操作期间，电源设置不会改变。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式