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91. 发明申请

WO2011025060A1 MEMORY MODULE AND VIDEO CAMERA 审中-公开
标题翻译：内存模块和视频摄像机
公开(公告)号：WO2011025060A1
公开(公告)日：2011-03-03
申请号：PCT/JP2010/065078
申请日：2010-08-27
申请人： Kabushiki Kaisha Toshiba , NAGAHARA, Yasuyuki , OZAWA, Isao
发明人： NAGAHARA, Yasuyuki , OZAWA, Isao
IPC分类号： G06K19/077 , H05K1/18
CPC分类号： G11C5/025 , G06F12/0246 , G06F17/5045 , G06F17/5068 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G11C5/04 , G11C16/00 , G11C29/48 , G11C2029/5602 , H05K1/0268 , H05K1/181 , H05K2201/10159 , H05K2201/10189 , H05K2201/10545 , H05K2203/162 , Y02P70/611
摘要： According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board 9; a controller 6 that is mounted either on an obverse side or a reverse side of the mounting board 9, and performs read and write control of the semiconductor memories; and a connector 3 that is deviated in a lateral direction from the controller 6 so as not to overlap the controller 6, is mounted either on the obverse side or the reverse side of the mounting board 9, and transfers a signal exchanged between the controller 6 and outside.
摘要翻译：根据实施例，提供了分别安装在安装板9的两侧的半导体存储器; 控制器6，其安装在安装板9的正面或反面上，并且执行半导体存储器的读和写控制; 并且从控制器6向横向方向偏离以不与控制器6重叠的连接器3安装在安装板9的正面或反面上，并且传送在控制器6之间交换的信号和外面。

92. 发明申请

WO2011014232A2 ENHANCED BLOCK COPY 审中-公开
标题翻译：增强块复制
公开(公告)号：WO2011014232A2
公开(公告)日：2011-02-03
申请号：PCT/US2010/002008
申请日：2010-07-16
申请人： MICRON TECHNOLOGY, INC. , NOBUNAGA, Dean, K.
发明人： NOBUNAGA, Dean, K.
IPC分类号： G11C16/06 , G11C16/34 , G11C16/10
CPC分类号： G11C5/025 , G06F12/0246 , G06F2212/7203 , G11C16/0483 , G11C16/105 , G11C19/00
摘要： The present disclosure includes methods and apparatus for an enhanced block copy. One embodiment includes reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts.
摘要翻译：本公开包括用于增强块拷贝的方法和装置。一个实施例包括从位于存储器件的第一部分的源块读取数据，以及将数据编程到位于存储器件的第二部分中的目标块。第一和第二部分通过跨越部分延伸的数据线通信地耦合。对于读取和编程动作中的至少一个，数据线在第一和第二部分之间通信地分离。

93. 发明申请

WO2010123978A1 REDUCED COMPLEXITY ARRAY LINE DRIVERS FOR 3D MATRIX ARRAYS 审中-公开
标题翻译：减少复杂的阵列线驱动器为3D矩阵阵列
公开(公告)号：WO2010123978A1
公开(公告)日：2010-10-28
申请号：PCT/US2010/031876
申请日：2010-04-21
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca
IPC分类号： G11C5/02 , G11C5/06 , G11C8/10 , G11C8/12 , G11C11/16 , G11C11/22 , G11C7/10 , G11C13/02 , G11C16/02
CPC分类号： G11C11/22 , G11C5/025 , G11C5/063 , G11C8/10 , G11C8/12 , G11C11/16 , G11C13/0002 , G11C13/0026 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of the first or second plurality of Y lines and one of the plurality of X lines, respectively. Substantially all of the first plurality and second plurality of Y lines are driven to a Y line unselect voltage. At least one selected Y line of the first plurality of Y lines is driven to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage.
摘要翻译：一种偏置非易失性存储器阵列的方法。非易失性存储器阵列包括第一和第二多个Y线，多个X线，第一和第二多个两个终端存储器单元。每个第一和第二存储器单元分别耦合到第一或第二多个Y线中的一个以及多个X线中的一个。基本上所有第一和第二多条Y线被驱动到Y线取消选择电压。第一多个Y线中的至少一个选择的Y线被驱动到Y线选择电压，同时浮置第一多个Y线的剩余Y线，同时驱动基本上所有第二多条Y线到Y线取消选择电压。

94. 发明申请

WO2010087892A2 A CIRCUIT FOR AND METHOD OF REDUCING POWER CONSUMPTION IN INPUT PORTS OF AN INTERGRATED CIRCUIT 审中-公开
标题翻译：降低集成电路输入端口功耗的方法及方法
公开(公告)号：WO2010087892A2
公开(公告)日：2010-08-05
申请号：PCT/US2009/065589
申请日：2009-11-23
申请人： XILINX, INC.
发明人： CONSTANTIN, Cical, I. , CULLEN, Edward
IPC分类号： G05F1/10
CPC分类号： G11C5/025 , G11C5/063 , G11C5/147
摘要： A circuit for reducing power consumption in input ports of an integrated circuit (102) is disclosed. The circuit comprises a plurality of receiver circuits (112, 114, 116, 118) of the integrated circuit (102) for receiving input signals coupled to the integrated circuit (102); and a bias current generator (122) coupled to the plurality of receiver circuits (112, 114, 116, 118), the bias current generator (122) providing a bias voltage for each receiver circuit of the plurality of receiver circuits (112, 114, 116, 118) to mirror the current in the bias current generator (122) in each of the receiver circuits (112, 114, 116, 118). A method of reducing power consumption in input ports of an integrated circuit (102) is also disclosed.
摘要翻译：公开了一种降低集成电路（102）输入端口功耗的电路。该电路包括用于接收耦合到集成电路（102）的输入信号的集成电路（102）的多个接收器电路（112,114,116,118）。以及耦合到所述多个接收器电路（112,114,116,118）的偏置电流发生器（122），所述偏置电流发生器（122）为所述多个接收器电路（112,114）中的每个接收器电路提供偏置电压，116,118,118,118,116,118），用于镜像每个接收器电路（112,114,116,118）中的偏置电流发生器（122）中的电流。还公开了一种降低集成电路（102）输入端口功耗的方法。

95. 发明申请

WO2009099626A1 MULTIPLE MEMORY CELLS AND METHOD 审中-公开
标题翻译：多个记忆细胞和方法
公开(公告)号：WO2009099626A1
公开(公告)日：2009-08-13
申请号：PCT/US2009/000738
申请日：2009-02-05
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun
发明人： LIU, Jun
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C13/0004 , C07D213/81 , C07D401/06 , C07D401/12 , C07D401/14 , G11C5/025 , G11C5/063 , G11C13/0023 , G11C13/003 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L27/1021
摘要： Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.
摘要翻译：显示了所描述的存储器件和方法，其提供了改进，包括改进的诸如读取和写入等操作的单元隔离。此外，示出了用于寻址和访问单元的方法和设备，其提供了管理具有与每个存取晶体管相关联的多个单元的器件的简单且有效的方式。多个单元设备的示例包括具有与每个存取晶体管相关联的多个单元的相变存储器件。

96. 发明申请

WO2009055031A1 THREE-DIMENSIONAL MEMORY MODULE ARCHITECTURES 审中-公开
标题翻译：三维存储器模块架构
公开(公告)号：WO2009055031A1
公开(公告)日：2009-04-30
申请号：PCT/US2008/012118
申请日：2008-10-23
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , MCLAREN, Moray , AHN, Jung Ho, , DAVIS, Alan Lynn, , BINKERT, Nathan Lorenzo, , JOUPPI, Norman Paul,
发明人： MCLAREN, Moray , AHN, Jung Ho, , DAVIS, Alan Lynn, , BINKERT, Nathan Lorenzo, , JOUPPI, Norman Paul,
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C13/04 , G11C2211/4016 , G11C2213/71 , H01L25/0657 , H01L25/18 , H01L2225/06534 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module (100,600,1200,1400) comprises at least one memory-controller layer (102,602,1204,1402) stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) (114,116) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller (401-404) and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer (602,1202). The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.
摘要翻译：本发明的各种实施例涉及堆叠的存储器模块。在本发明的一个实施例中，存储器模块（100,600,1200,1400）包括与至少一个存储器层堆叠的至少一个存储器控制器层（102,602,1204,1402）。通过通孔（例如，通过硅通孔）（114,116）精细地延伸通过堆叠大致垂直于至少一个存储器控制器的表面延伸，从而提供至少一个存储器控制器（401-404）与至少一个存储器控制器内存层。此外，存储器控制器层包括被配置为向存储器模块传送数据和从存储器模块传送数据的至少一个外部接口。此外，存储器模块可以包括光学层（602,1202）。光学层可以被包括在堆叠中并且具有总线波导以将数据传送到至少一个存储器控制器和从至少一个存储器控制器传送数据。外部接口可以是与光学层接口的光学外部接口。

97. 发明申请

WO2007124208A3 MEMORY CIRCUIT 审中-公开
标题翻译：存储器电路
公开(公告)号：WO2007124208A3
公开(公告)日：2008-11-13
申请号：PCT/US2007063280
申请日：2007-03-05
申请人： FREESCALE SEMICONDUCTOR INC , RUSSELL ANDREW C
发明人： RUSSELL ANDREW C
IPC分类号： G11C5/06
CPC分类号： G11C5/14 , G11C5/025
摘要： A memory (10) includes a plurality of memory arrays. Each of the plurality of memory arrays includes a plurality of sub-arrays (52-129). A plurality of power supply conductors (158, 160) are provided over the memory (10) for supplying power to the plurality of memory arrays. When accessing the memory (10) to simultaneously read a plurality of bits from the memory (10), the sub-arrays (52, 129) are accessed so as to provide a relatively uniform current demand on the plurality of power supply conductors. In one embodiment, the accessed sub-arrays (52, 129) are organized so that sides, or edges, of each accessed sub-array are not adjacent to each other.
摘要翻译：存储器（10）包括多个存储器阵列。多个存储器阵列中的每一个包括多个子阵列（52-129）。多个电源导体（158,160）设置在存储器（10）上，用于向多个存储器阵列供电。当访问存储器（10）以同时从存储器（10）读取多个位时，子阵列（52,129）被访问以便在多个电源导体上提供相对均匀的电流需求。在一个实施例中，所访问的子阵列（52,129）被组织成使得每个被访问的子阵列的边或边不彼此相邻。

98. 发明申请

WO2008064466A1 NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE 审中-公开
标题翻译：非易失性存储器串行核心架构
公开(公告)号：WO2008064466A1
公开(公告)日：2008-06-05
申请号：PCT/CA2007/002125
申请日：2007-11-26
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki
发明人： KIM, Jin-Ki
IPC分类号： G11C7/10 , G11C16/02 , G11C8/18 , H03M9/00
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0659 , G06F3/0679 , G11C5/025 , G11C7/1006 , G11C7/1033 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1072 , G11C7/12 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/32 , G11C2207/107 , G11C2216/14 , G11C2216/20 , G11C2216/30
摘要： A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
摘要翻译：一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。记忆库分为两半，每半部分分为上下扇区。每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。具有集成自列解码电路的共享二维页面缓冲器最小化每个存储体的电路和芯片面积开销，并且串行数据路径核心减少通常用于布线宽数据总线的芯片面积。因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。

99. 发明申请

WO2007051795A1 METHOD AND APPARATUS FOR VARYING THE PROGRAMMING DURATION AND/OR VOLTAGE OF AN ELECTRICALLY FLOATING BODY TRANSISTOR, AND MEMORY CELL ARRAY IMPLEMENTING SAME 审中-公开
标题翻译：改变电浮动体晶体管的编程持续时间和/或电压的方法和装置，以及实现其的存储器单元阵列
公开(公告)号：WO2007051795A1
公开(公告)日：2007-05-10
申请号：PCT/EP2006/067968
申请日：2006-10-31
申请人： INNOVATIVE SILICON S.A. , POPOFF, Gregory A. , DE CHAMPS, Paul , DAGHIGHIAN, Hamid
发明人： POPOFF, Gregory A. , DE CHAMPS, Paul , DAGHIGHIAN, Hamid
IPC分类号： G11C11/406
CPC分类号： G11C5/025 , G11C7/14 , G11C7/22 , G11C11/404 , G11C11/406 , G11C11/4074 , G11C11/4076 , G11C11/4099 , G11C2211/4016 , G11C2211/4061 , G11C2211/4068
摘要： There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating a semiconductor memory cells of a memory cell array, including electrically floating body transistors in which an electrical charge is stored in the body of the transistor. In one aspect, the present inventions are directed to one or more independently controllable parameters of a memory operation (for example, restore, write, refresh), to program or write a data state into a memory cell. In one embodiment, the parameter is the amount of time of programming or writing a predetermined data state into a memory cell. In another embodiment, the controllable parameter is the amplitude of the voltage of the control signals applied to the gate, drain region and/or source region during programming or writing a predetermined data state into a memory cell. Indeed, the controllable parameters may be both temporal and voltage amplitude. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).
摘要翻译：这里描述的许多发明以及这些发明的许多方面和实施例，例如用于读取，写入和/或操作存储单元阵列的半导体存储器单元的电路和技术，包括电浮动体晶体管，其中电气电荷存储在晶体管的体内。在一个方面，本发明涉及存储器操作（例如，恢复，写入，刷新）的一个或多个可独立控制的参数，以将数据状态编程或写入存储器单元。在一个实施例中，参数是将预定数据状态编程或写入存储单元的时间量。在另一个实施例中，可控参数是在将预定数据状态编程或写入存储单元期间施加到栅极，漏极区域和/或源极区域的控制信号的电压的幅度。实际上，可控参数可以是时间和电压振幅。值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件（例如，分立存储器）的一部分。

100. 发明申请

WO2006071836A1 MEMORY MODULE ROUTING 审中-公开
标题翻译：内存模块路由
公开(公告)号：WO2006071836A1
公开(公告)日：2006-07-06
申请号：PCT/US2005/046995
申请日：2005-12-21
申请人： INTEL CORPORATION , SPRIETSMA, John , LEDDIGE, Michael
发明人： SPRIETSMA, John , LEDDIGE, Michael
IPC分类号： H05K1/02 , H05K1/00 , H05K1/18
CPC分类号： G11C5/025 , G11C5/04 , H05K1/0298 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , Y02P70/611
摘要： A memory module circuit board includes a first surface adapted to couple a first plurality of memory devices (624), a plurality of signal lines (626), and a command and address bus (636, 642) coupled to the signal lines. The command and address bus is routed from the signal lines and adapted to couple to at least one of the first plurality of memory devices in a manner that does not require the command and address bus lines to turn more than approximately ninety degrees before coupling to the at least one of the first plurality of memory devices.
摘要翻译：存储器模块电路板包括适于耦合第一多个存储器件（624），多个信号线（626）以及耦合到信号线的命令和地址总线（636,642）的第一表面。命令和地址总线从信号线路由并且适于以不要求命令和地址总线转过多于九十度的方式耦合到第一多个存储器件中的至少一个，在耦合到所述第一多个存储器件中的至少一个。

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