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91. 发明申请

WO2017155612A1 WAFER PROCESSING TOOL HAVING A MICRO SENSOR 审中-公开
标题翻译：具有微型传感器的晶圆加工工具
公开(公告)号：WO2017155612A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/014176
申请日：2017-01-19
申请人： APPLIED MATERIALS, INC.
发明人： TEDESCHI, Leonard
IPC分类号： H01L21/66 , H01L21/67
CPC分类号： H01L22/26 , C23C16/52 , H01L21/0262 , H01L22/12
摘要： Embodiments include devices and methods for detecting material deposition and material removal performed by a wafer processing tool. In an embodiment, one or more micro sensors mounted on a process chamber of the wafer processing tool are capable of operating under vacuum conditions and/or may measure material deposition and removal rates in real-time during a plasma-less wafer fabrication process. Other embodiments are also described and claimed.
摘要翻译：实施例包括用于检测由晶片处理工具执行的材料沉积和材料去除的装置和方法。在一个实施例中，安装在晶片处理工具的处理室上的一个或多个微传感器能够在真空条件下操作和/或可以在无等离子晶片制造处理期间实时测量材料沉积和去除速率。其他实施例也被描述和要求保护。

92. 发明申请

WO2017131875A1 SELF-AWARE PRODUCTION WAFERS 审中-公开
标题翻译：自我意识生产晶片
公开(公告)号：WO2017131875A1
公开(公告)日：2017-08-03
申请号：PCT/US2016/066223
申请日：2016-12-12
申请人： APPLIED MATERIALS, INC.
发明人： TEDESCHI, Leonard , RAMASWAMY, Kartik
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L22/26
摘要： Embodiments include a self-aware substrate and methods for utilizing a self-aware substrate. In one embodiment, a method of processing a self-aware substrate may include initiating a processing operation on the self-aware substrate. The processing operation may be any processing operation used in the fabrication of functioning devices on a production substrate. The method may further include receiving output signals from one or more sensors on the self-aware substrate. In some embodiments, the one or more sensors are formed on non-production regions of the substrate. The method may further include comparing the output signals to an endpoint criteria that is associated with one or more processing conditions. For example, the endpoint criteria may be associated with processing conditions such as film thickness. The method may further include ending the processing operation when the endpoint criteria is satisfied.
摘要翻译：实施例包括自我感知基板和用于利用自我感知基板的方法。在一个实施例中，处理自知觉基板的方法可以包括在自知觉基板上启动处理操作。处理操作可以是在制造基板上的功能器件的制造中使用的任何处理操作。该方法可以进一步包括接收来自自感知基板上的一个或多个传感器的输出信号。在一些实施例中，一个或多个传感器形成在衬底的非生产区域上。该方法可以进一步包括将输出信号与和一个或多个处理条件相关联的端点标准进行比较。例如，终点标准可能与处理条件如薄膜厚度有关。该方法还可以包括在满足端点标准时结束处理操作。

93. 发明申请

WO2017111958A1 TRANSISTORS HAVING ULTRA THIN FIN PROFILES AND THEIR METHODS OF FABRICATION 审中-公开
标题翻译：具有超薄鳍型的晶体管及其制造方法
公开(公告)号：WO2017111958A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067449
申请日：2015-12-22
申请人： INTEL CORPORATION
发明人： GARDNER, Sanaz K. , RACHMADY, Willy , LE, Van H. , METZ, Matthew V. , KIM, Seiyon , AGRAWAL, Ashish , KAVALIEROS, Jack T.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0673 , H01L29/107 , H01L29/66439 , H01L29/66469 , H01L29/775
摘要： A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.
摘要翻译：描述了具有超薄鳍形轮廓的晶体管及其制造方法。该晶体管包括具有在半导体衬底上形成的绝缘层的半导体衬底。鳍从半导体衬底延伸。鳍具有半导体衬底上的亚鳍部分和亚鳍部分上的主动鳍部分。亚鳍部分布置在绝缘层中形成的沟槽中。亚鳍部分包括III-V半导体材料，有源鳍部分包括IV族半导体材料。

94. 发明申请

WO2017111914A1 LOW BAND GAP SEMICONDUCTOR DEVICES HAVING REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL) AND THEIR METHODS OF FABRICATION 审中-公开
标题翻译：低带隙半导体器件具有栅极泄漏泄漏减少（GIDL）及其制造方法
公开(公告)号：WO2017111914A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067168
申请日：2015-12-21
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert , KAVALIEROS, Jack T. , RACHMADY, Willy , METZ, Matthew V. , LE, Van H. , KIM, Seiyon , CHU-KUNG, Benjamin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/775 , H01L29/785
摘要： Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.
摘要翻译：本发明的实施例针对低带隙半导体器件。在示例中，器件包括形成在衬底上方的第一半导体材料，第一半导体材料具有第一带隙。栅极介电层位于第一半导体材料的表面上。栅电极在栅极介电层上。一对源极/漏极区位于栅电极的相对侧上。沟道设置在第一半导体材料中位于一对源极/漏极区域之间并且在栅极电极下方。该对源极/漏极区域包括具有第二带隙的第二半导体材料以及具有第三带隙的第三半导体材料。第二半导体材料在第一半导体材料和第三半导体材料之间，并且第二带隙大于第一带隙。

95. 发明申请

WO2016160104A1 MASK ETCH FOR PATTERNING 审中-公开
标题翻译：掩蔽蚀刻
公开(公告)号：WO2016160104A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/014366
申请日：2016-01-21
申请人： APPLIED MATERIALS, INC.
发明人： LEE, Gene , CHEN, Lucy
IPC分类号： H01L21/027
CPC分类号： H01L21/31133 , C23C16/50 , C23C16/52 , H01L21/02274 , H01L21/0332 , H01L21/31116 , H01L21/31122 , H01L21/31144 , H01L21/67069 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： A hard mask layer is deposited on a feature layer over a substrate. The hard mask layer comprises an organic mask layer. An opening in the organic mask layer is formed using a first gas comprising a halogen element at a first temperature greater than a room temperature to expose a portion of the feature layer. In one embodiment, a gas comprising a halogen element is supplied to a chamber. An organic mask layer on an insulating layer over a substrate is etched using the halogen element at a first temperature to form an opening to expose a portion of the insulating layer.
摘要翻译：硬掩模层沉积在衬底上的特征层上。硬掩模层包括有机掩模层。在大于室温的第一温度下，使用包含卤素元素的第一气体形成有机掩模层中的开口，以暴露特征层的一部分。在一个实施方案中，将包含卤素元素的气体供应到室。使用卤素元素在第一温度下蚀刻在衬底上的绝缘层上的有机掩模层，以形成露出绝缘层的一部分的开口。

96. 发明申请

WO2016039935A1 FLOWABLE FILM PROPERTIES TUNING USING IMPLANTATION 审中-公开
标题翻译：可流动电影属性使用植入调谐
公开(公告)号：WO2016039935A1
公开(公告)日：2016-03-17
申请号：PCT/US2015/045393
申请日：2015-08-14
申请人： APPLIED MATERIALS, INC.
发明人： YIEH, Ellie Y. , GODET, Ludovic , XUE, Jun , NEMANI, Srinivas D. , LI, DongQing (Karen) , CHEN, Erica
IPC分类号： H01L21/205 , H01L21/31
CPC分类号： H01L21/26506 , H01L21/02164 , H01L21/02271 , H01L21/02321 , H01L21/02323 , H01L21/0337 , H01L21/3065 , H01L21/31155 , H01L29/6653 , H01L29/66545 , H01L29/66795
摘要： Species are supplied to a flowable layer over a substrate. A property of the flowable layer is modified by implanting the species to the flowable layer. The property comprises a density, a stress, a film shrinkage, an etch selectivity, or any combination thereof.
摘要翻译：物质被提供到基底上的可流动层。可流动层的性质通过将物种注入可流动层来改变。该性质包括密度，应力，薄膜收缩率，蚀刻选择性或其任何组合。

97. 发明申请

WO2016014168A1 SINGLE PLATFORM, MULTIPLE CYCLE SPACER DEPOSITION AND ETCH 审中-公开
标题翻译：单平台，多个循环间隔沉积和蚀刻
公开(公告)号：WO2016014168A1
公开(公告)日：2016-01-28
申请号：PCT/US2015/035666
申请日：2015-06-12
申请人： APPLIED MATERIALS, INC.
发明人： CHEN, Hao , YING, Chentsau (Chris) , NEMANI, Srinivas D. , YIEH, Ellie Y.
IPC分类号： H01L21/02
CPC分类号： H01L21/3086 , C23C16/04 , C23C16/34 , C23C16/345 , C23C16/45544 , C23C16/50 , H01J37/32009 , H01J37/32082 , H01L21/0217 , H01L21/02274 , H01L21/0228 , H01L21/0337 , H01L21/28132 , H01L21/30604 , H01L21/3065 , H01L21/31116 , H01L21/32139 , H01L21/67069 , H01L21/67207 , H01L21/67742
摘要： A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed.
摘要翻译：多周期间隔物的第一部分形成在衬底上的图案化特征的侧壁上。使用第一等离子体工艺在第一部分上沉积间隔层。使用第二等离子体工艺蚀刻间隔层以在第一部分上形成多循环间隔物的第二部分。连续重复包括沉积和蚀刻间隔层的循环直到形成多循环间隔物。

98. 发明申请

WO2015195488A1 POLISHING PAD HAVING POROGENS WITH LIQUID FILLER 审中-公开
标题翻译：具有液体填料的抛光垫
公开(公告)号：WO2015195488A1
公开(公告)日：2015-12-23
申请号：PCT/US2015/035662
申请日：2015-06-12
申请人： NEXPLANAR CORPORATION
发明人： LEFEVRE, Paul Andre , ALLISON, William C.
IPC分类号： B24B37/24 , B24B37/26
CPC分类号： B24B37/24 , B24B37/205 , B24B37/26 , B24D3/32
摘要： Polishing pads having porogens with liquid filler and methods of fabricating polishing pads having porogens with liquid filler are described. In an example, a polishing pad for polishing a substrate includes a polishing body having a polymer matrix and a plurality of porogens dispersed throughout the polymer matrix. Each of the plurality of porogens has a shell with a liquid filler. The liquid filler has a boiling point less than 100 degrees Celsius at a pressure of 1 atm, a density less than water, or both.
摘要翻译：描述了具有带有液体填料的致孔剂的抛光垫和用液体填料制造具有致孔剂的抛光垫的方法。在一个实例中，用于抛光衬底的抛光垫包括具有分散在整个聚合物基体中的聚合物基质和多个致孔剂的抛光体。多个致孔剂中的每一个具有带有液体填料的壳。液体填充剂的沸点低于100摄氏度，压力为1个大气压，密度小于水或两者。

99. 发明申请

WO2015179194A1 PRESENCE SENSING AND POSITION CORRECTION FOR WAFER ON A CARRIER RING 审中-公开
标题翻译：在载波环上存在感测和位置校正
公开(公告)号：WO2015179194A1
公开(公告)日：2015-11-26
申请号：PCT/US2015/030656
申请日：2015-05-13
申请人： APPLIED MATERIALS, INC.
发明人： MAZZOCCO, John , GREENBERG, Daniel
IPC分类号： H01L21/68
CPC分类号： B25J9/1697 , B25J9/1612 , B25J15/0014 , G05B19/401 , G05B2219/37002 , G05B2219/37608 , G06T7/0004 , G06T7/66 , G06T7/68 , G06T2207/10004 , G06T2207/30164 , Y10S901/02 , Y10S901/46 , Y10S901/47
摘要： Embodiments of the invention include apparatuses and systems for determining the position of a carrier ring assembly supported by an end effector. In an embodiment, the position of the carrier ring assembly is determined by passing the carrier ring assembly through a plurality of through beam sensors. As the carrier ring passes through the sensors, a plurality of sensor transitions along points on the carrier ring assembly are detected. Each sensor transition indicates that one of the through beam sensors changed from an unblocked state to a blocked state, or changed from an blocked state to an unblocked state. The position of the end effector is recorded at each sensor transition and is associated with the sensor transition that caused the end effector position to be recorded. A position of the carrier ring assembly is then calculated from the plurality of sensor transitions and their associated end effector positions.
摘要翻译：本发明的实施例包括用于确定由端部执行器支撑的载体环组件的位置的装置和系统。在一个实施例中，通过使承载环组件穿过多个通过梁传感器来确定承载环组件的位置。当载体环通过传感器时，检测到沿着载体环组件上的点的多个传感器转变。每个传感器转换指示一个通过光束传感器从未阻塞状态改变到阻塞状态，或从阻塞状态改变为未阻塞状态。在每个传感器转换处记录末端执行器的位置，并且与导致末端执行器位置被记录的传感器转换相关联。然后从多个传感器转变及其相关的末端执行器位置计算载体环组件的位置。

100. 发明申请

WO2015179192A1 COOLING PEDESTAL FOR DICING TAPE THERMAL MANAGEMENT DURING PLASMA DICING 审中-公开
标题翻译：在等离子体处理期间冷却热带管道热管理
公开(公告)号：WO2015179192A1
公开(公告)日：2015-11-26
申请号：PCT/US2015/030613
申请日：2015-05-13
申请人： APPLIED MATERIALS, INC.
发明人： NANGOY, Roy, C.
IPC分类号： H01L21/3065 , H01L21/301
CPC分类号： H01L21/82 , H01J37/32091 , H01J37/32715 , H01J37/32724 , H01L21/3065 , H01L21/3081 , H01L21/31127 , H01L21/67069 , H01L21/67207 , H01L21/673 , H01L21/78
摘要： Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber. The plasma etch chamber also includes a cathode assembly disposed below the plasma source. The cathode assembly includes a cooling RF-powered chuck for supporting an inner portion of a backside of a substrate carrier. The cathode assembly also includes a cooling RF-isolated support surrounding but isolated from the RF-powered chuck. The RF-isolated support is for supporting an outer portion of the backside of the substrate carrier.
摘要翻译：对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。在一个示例中，等离子体蚀刻室包括设置在等离子体蚀刻室的上部区域中的等离子体源。等离子体蚀刻室还包括设置在等离子体源下方的阴极组件。阴极组件包括用于支撑衬底载体的背面的内部的冷却RF供电的卡盘。阴极组件还包括围绕但与RF供电的卡盘隔离的冷却RF隔离支架。 RF隔离支撑件用于支撑衬底载体的背面的外部部分。

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