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1. 发明申请

WO2016089291A1 MULTI-STAGE FREQUENCY DIVIDERS AND POLY-PHASE SIGNAL GENERATORS 审中-公开
标题翻译：多级频分复用器和多相信号发生器
公开(公告)号：WO2016089291A1
公开(公告)日：2016-06-09
申请号：PCT/SE2015/051296
申请日：2015-12-02
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： BAGGER, Reza
IPC分类号： H03K21/10 , H03K23/48 , H03K23/42 , H03K3/356 , H03K3/3562
CPC分类号： H03K21/10 , H03K3/356104 , H03K3/356139 , H03K3/35625 , H03K5/15066 , H03K19/20 , H03K23/425 , H03K23/483 , H04B1/40
摘要： An electronic latch circuit (100), a 4–phase signal generator, a multi–stage frequency divider and a poly–phase signal generator are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106) and a second output (Y, 107). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on the input signals' level at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The 4–phase signal generator is built with two electronic latch circuits (100). The multi–stage frequency dividers and poly–phase signal generators comprise a plurality of the electronic latch circuits (100) and 4–phase signal generators (300).
摘要翻译：公开了电子锁存电路（100），4相信号发生器，多级分频器和多相信号发生器。电子锁存电路（100）包括包括第一输出（X，106）和第二输出（Y，107）的输出电路（105）。电子锁存电路（100）还包括包括第一输入（A，102），第二输入（B，103）和时钟信号输入（CLK，104）的输入电路（101）。电子锁存电路（100）被配置为基于输入电路（101）的输入（A，B，CLK）处的输入信号电平和输出电路（105）的当前状态来改变状态。 4相信号发生器由两个电子锁存电路（100）构成。多级分频器和多相信号发生器包括多个电子锁存电路（100）和4相信号发生器（300）。

2. 发明申请

WO2007004181A2 MULTI-BIT PROGRAMMABLE FREQUENCY DIVIDER 审中-公开
标题翻译：多位可编程分频器
公开(公告)号：WO2007004181A2
公开(公告)日：2007-01-11
申请号：PCT/IB2006052215
申请日：2006-06-30
申请人： KONINKL PHILIPS ELECTRONICS NV , PHILIPS CORP , SONG WENYI , JOORDENS GEERTJAN
发明人： SONG WENYI , JOORDENS GEERTJAN
IPC分类号： H03K23/48
CPC分类号： H03K23/665 , H03K23/425 , H03K23/542
摘要： A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at the end of every output clock. Each divisor bit is gated to a D-input through a respective data multiplexer controlled by a clock output. A run/initialize mode controller receives the input frequency and produces the divided output frequency and controls the timing of the re-initialization.
摘要翻译：一个多位可编程模块化数字分频器将输入频率除以m位整数除数以产生输出频率。整数除数在每个输出时钟结束时用除数输入重新初始化M个触发器级。每个除数位通过由时钟输出控制的相应数据复用器选通D输入。运行/初始化模式控制器接收输入频率并产生分频输出频率并控制重新初始化的时序。

3. 发明申请

WO2016089292A1 POWER EFFICIENT HIGH SPEED LATCH CIRCUITS AND SYSTEMS 审中-公开
标题翻译：功率有效的高速锁存电路和系统
公开(公告)号：WO2016089292A1
公开(公告)日：2016-06-09
申请号：PCT/SE2015/051298
申请日：2015-12-02
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： BAGGER, Reza
IPC分类号： H03K21/10 , H03K23/48 , H03K23/42 , H03K3/356 , H03K3/3562
CPC分类号： H03K21/10 , H03K3/356104 , H03K3/356139 , H03K3/35625 , H03K5/15066 , H03K19/20 , H03K23/425 , H03K23/483 , H04B1/40
摘要： The present invention relates to a combiner latch circuit and a latching system for generation of one phase differential signal pair or two phase differential signal pairs. The scope of the applications ranges from division and frequency generation in prescalers to phase and frequency generation in mixer's transceivers for high speed wireless applications. The combiner latch circuit 700 comprises an input circuit 701 with an input A 702, an input B 703, a clock input CLK 704, and an inverted clock input CLK705, an output circuit 706with a differential output X, Y 707,708. The input circuit 701 is connected to the output circuit 706, and configured to select a state of the output circuit 706 from a group of: a fourth state (S4) comprising the differential output X=1, Y=0 of the differential output X, Y 707,708, a fifth state (S5) comprising the differential output X=0,Y=1 of the differential output X, Y 707,708. The input circuit 701 is further configured to select the fourth state S4 if the input A=0 and the input B=1 and the clock input CLK 704 encounter a leading edge from 0 to 1 and the output circuit is in the fifth state S5, and select the fifth state S5 if the input A=1 and the input B=0 and the clock input CLK 704encounter a leading edge from 0 to 1 and the output circuit is in the fourth state S4.
摘要翻译：本发明涉及用于产生一相差分信号对或两相差分信号对的组合器锁存电路和闭锁系统。应用范围从预分频器的分频和频率生成到混频器收发器中的高频无线应用的相位和频率产生。组合器锁存电路700包括具有输入A 702，输入B 703，时钟输入CLK 704和反相时钟输入CLK705的输入电路701，具有差分输出X的输出电路706，Y 707,708。输入电路701连接到输出电路706，并且被配置为从包括差分输出X的差分输出X = 1，Y = 0的第四状态（S4）中选择输出电路706的状态，Y 707,708，包括差分输出X = 0，差分输出X的Y = 1的第五状态（S5），Y 707,708。输入电路701还被配置为：如果输入A = 0且输入B = 1并且时钟输入CLK 704的前沿从0到1，并且输出电路处于第五状态S5，则选择第四状态S4，并且如果输入A = 1并且输入B = 0并且时钟输入CLK 704en从0到1的前沿，并且输出电路处于第四状态S4，则选择第五状态S5。

4. 发明申请

WO2006051490A1 FREQUENCY DIVISION BY ODD INTEGERS 审中-公开
标题翻译： ODD整数的频率划分
公开(公告)号：WO2006051490A1
公开(公告)日：2006-05-18
申请号：PCT/IB2005/053679
申请日：2005-11-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DE BEEK, Remco, C., H. , LEENAERTS, Dominicus, M., W.
发明人： VAN DE BEEK, Remco, C., H. , LEENAERTS, Dominicus, M., W.
IPC分类号： H03K23/48
CPC分类号： H03K23/483
摘要： The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CLl) frequency by an odd integer. A digital value is shifted into a set of latches based on the clock signal (CLl) and kept there a predetermined number of half clock cycles. The value is shifted into a following latch delayed with half a clock cycle of the clock signal compared with a previous latch. Then a first (Ql) and a second (Q6) intermediate signal, each provided through information stored in a latch, are interpolated for forming said first output signal (O Q). Because of this it is possible to provide an output signal having edges displaced from clock signal edges, thus allowing a higher resolution than the original clock signal has and in particular, enabling quadrature outputs from a standard odd-integer frequency divider.
摘要翻译：本发明涉及一种用于提供具有通过将时钟信号（CL1）频率除以奇整数而获得的频率的至少第一输出信号（O Q）的方法和装置。数字值根据时钟信号（CL1）移入一组锁存器，并保持预定数量的半个时钟周期。与先前的锁存器相比，该值被移位到延迟了时钟信号的半个时钟周期的后续锁存器。然后插入通过存储在锁存器中的信息提供的第一（Q1）和第二（Q6）中间信号，以形成所述第一输出信号（O Q）。因此，可以提供具有从时钟信号边缘移位的边缘的输出信号，从而允许比原始时钟信号具有更高的分辨率，并且特别地，允许来自标准奇整数分频器的正交输出。

5. 发明申请

WO2011028157A1 A HIGH-SPEED NON-INTEGER FREQUENCY DIVIDER CIRCUIT 审中-公开
标题翻译：高速非整数分频分频电路
公开(公告)号：WO2011028157A1
公开(公告)日：2011-03-10
申请号：PCT/SE2009/050990
申请日：2009-09-02
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , NYLÉN, Tomas , MALMCRONA, Adam
发明人： NYLÉN, Tomas , MALMCRONA, Adam
IPC分类号： H03K23/54 , H03K23/42 , H03K23/48 , H03K23/68 , H03L7/197 , H03K23/40
CPC分类号： H03L7/197 , H03K23/425 , H03K23/546
摘要： The invention relates to a high-speed non-integer frequency divider circuit for use in generating frequencies in a communication device, comprising: at least four bi-stable memory devices each having an input terminal, a clock terminal and an output terminal for outputting an output signal. The high-speed non-integer frequency divider circuit is characterized in that the at least four bi-stable memory devices are arranged in a cascaded chain such that each bi-stable memory device following the first bi-stable memory device receives the output signal of a previous bi-stable memory device in the cascaded chain at its input terminal and such that at least one of the output signals of the last bi-stable memory device is used to control the input terminal of the first bi-stable memory device, and in that the frequency divider circuit further comprises a clocking arrangement adapted to provide an in-phase clock signal, a quadrature clock signal, an inverse of the in-phase clock signal and an inverse of the quadrature clock signal to the clock terminals of each of the at least four bi-stable memory devices such that a combination of output signals from the at least bi-stable memory devices produces a frequency divided output signal of the frequency divider circuit having a frequency division ratio of fourths of the frequency of the in-phase clock signal. The invention also relates to a frequency synthesizer and a communication device.
摘要翻译：本发明涉及用于在通信设备中产生频率的高速非整数分频器电路，包括：至少四个双稳态存储器件，每个具有输入端，时钟端和输出端，输出信号。高速非整数分频器电路的特征在于，至少四个双稳态存储器件布置在级联链中，使得跟随第一双稳态存储器件的每个双稳态存储器件接收到在其输入端子处的级联链中的先前双稳态存储器件，并且使得最后的双稳态存储器件的输出信号中的至少一个用于控制第一双稳态存储器件的输入端，以及分频器电路还包括时钟配置，其适于提供同相时钟信号，正交时钟信号，同相时钟信号的反相和正交时钟信号的倒数到每个时钟信号的时钟端子所述至少四个双稳态存储器件使得来自至少双稳态存储器件的输出信号的组合产生分频器电路的分频输出信号，其具有频率同相时钟信号频率的四分之一的分辨率。本发明还涉及频率合成器和通信设备。

6. 发明申请

WO1990008428A1 HIGH SPEED PRESCALER 审中-公开
标题翻译：高速预分机
公开(公告)号：WO1990008428A1
公开(公告)日：1990-07-26
申请号：PCT/US1990000161
申请日：1990-01-16
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , HEROLD, Barry, Wayne , TAHERNIA, Omid
IPC分类号： H03K23/48
CPC分类号： H03K23/667
摘要： A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages (outputs at 10, 12, 14, 16, 18). When a modulas control signal (MC) is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal (MC) is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry (60, 62, 64, 68, 70) forces the last three stages to change states simultaneously.

7. 发明申请

WO2016089275A1 AN ELECTRONIC LATCH CIRCUIT AND A GENERIC MULTI-PHASE SIGNAL GENERATOR 审中-公开
标题翻译：电子锁芯电路和一般的多相信号发生器
公开(公告)号：WO2016089275A1
公开(公告)日：2016-06-09
申请号：PCT/SE2015/050489
申请日：2015-05-04
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： BAGGER, Reza
IPC分类号： H03K21/10 , H03K23/48 , H03K23/42 , H03K3/356
CPC分类号： H03K21/10 , H03K3/356104 , H03K3/356139 , H03K3/35625 , H03K5/15066 , H03K19/20 , H03K23/425 , H03K23/483 , H04B1/40
摘要： An electronic latch circuit (100) and a multi−phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The multi−phase signal generator (300) comprises a plurality N of the electronic latch circuit (100) for generating N phase signals with individual phases. The plurality N of the electronic latch circuit (100) are cascaded with each other.
摘要翻译：公开了电子锁存电路（100）和多相信号发生器（300）。电子锁存电路（100）包括包括第一输出（X，106），第二输出（Y，107）和第三输出（Z，108）的输出电路（105）。电子锁存电路（100）还包括包括第一输入（A，102），第二输入（B，103）和时钟信号输入（CLK，104）的输入电路（101）。电子锁存电路（100）被配置为基于输入电路（101）的输入（A，B，CLK）和输出电路（105）的当前状态的输入信号来改变状态。多相信号发生器（300）包括用于产生具有各相的N相信号的多个电子锁存电路（100）。电子锁存电路（100）的多个N彼此级联。

8. 发明申请

WO2002069499A3 DIVIDE-BY-THREE CIRCUIT 审中-公开
公开(公告)号：WO2002069499A3
公开(公告)日：2002-09-06
申请号：PCT/US2001/051436
申请日：2001-10-25
申请人： QUALCOMM INCORPORATED
发明人： SUN, Bo
IPC分类号： H03K23/48
摘要： An in-phase clock signal CLK-I drives a first pair of connected data flip-flops (DFFs) (302) and (308), with feedback through a NOR gate (310) and output through an in-phase OR gate (320). The output signal OUT-I is a clock signal with a third of the frequency of CLK-I. A quadrature-phase dock signal CLK-Q drives a second pair of (DFFs) (504) and (506), with output through a quadrature OR gate (508). The output signal OUT-Q is a clock signal with a third of the frequency of CLK-Q, and in quadrature with OUT-I.

9. 发明申请

WO2002069499A2 DIVIDE-BY-THREE CIRCUIT 审中-公开
标题翻译：三线电路
公开(公告)号：WO2002069499A2
公开(公告)日：2002-09-06
申请号：PCT/US2001/051436
申请日：2001-10-25
申请人： QUALCOMM INCORPORATED
发明人： SUN, Bo
IPC分类号： H03K23/48
CPC分类号： H03K23/544 , H03K21/10
摘要： An in-phase clock signal CLK-I drives a first pair of connected data flip-flops (DFFs) (302) and (308), with feedback through a NOR gate (310) and output through an in-phase OR gate (320). The output signal OUT-I is a clock signal with a third of the frequency of CLK-I. A quadrature-phase dock signal CLK-Q drives a second pair of (DFFs) (504) and (506), with output through a quadrature OR gate (508). The output signal OUT-Q is a clock signal with a third of the frequency of CLK-Q, and in quadrature with OUT-I.
摘要翻译：同相时钟信号CLK-I通过NOR门（310）的反馈驱动第一对连接的数据触发器（DFF）（302）和（308），并通过同相或门（320）输出）。输出信号OUT-I是具有CLK-1频率的三分之一的时钟信号。通过正交或门（508）的输出，正交相位停靠信号CLK-Q驱动第二对（DFF）（504）和（506）。输出信号OUT-Q是具有CLK-Q频率的三分之一的时钟信号，并且与OUT-I正交。

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