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1. 发明申请

WO2008037397A1 METHOD AND SYSTEM FOR SELECTING A DATA TRANSMISSION RATE 审中-公开
标题翻译：用于选择数据传输速率的方法和系统
公开(公告)号：WO2008037397A1
公开(公告)日：2008-04-03
申请号：PCT/EP2007/008221
申请日：2007-09-21
申请人： KONINKLIJKE KPN N.V. , LUTHRA, Vinod
发明人： LUTHRA, Vinod
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L12/5601 , H04L12/2859 , H04L47/15 , H04L47/70 , H04L47/724 , H04L47/822 , H04L47/825 , H04L63/08 , H04L2012/5606 , H04L2012/561 , H04L2012/5615 , H04L2012/5616 , H04L2012/5618 , H04L2012/5634 , H04L2012/5636
摘要： The invention relates to a method and system for selecting a data transmission rate in a broadband network (3). The broadband network is connected to an access network (2) for providing access for user equipment (4) to the broadband network. Rate information is received from the user equipment. The rate information comprises a data transmission rate for data transmission over the access network. Thereafter, a data transmission rate for data transmission over the broadband network is selected. The selected data transmission rate for the broadband network is preferably less than or substantially equal to the data transmission rate for data transmission over the access network.
摘要翻译：本发明涉及一种在宽带网络中选择数据传输速率的方法和系统（3）。宽带网络连接到接入网络（2），用于向宽带网络提供用户设备（4）的接入。从用户设备接收速率信息。速率信息包括用于通过接入网络进行数据传输的数据传输速率。此后，选择通过宽带网络进行数据传输的数据传输速率。所选择的宽带网络的数据传输速率优选地小于或基本上等于用于接入网络上的数据传输的数据传输速率。

2. 发明申请

WO2003061232A1 CORE WIRELESS ENGINE 审中-公开
标题翻译：核心无线发动机
公开(公告)号：WO2003061232A1
公开(公告)日：2003-07-24
申请号：PCT/CA2003/000002
申请日：2003-01-02
申请人： SIERRA WIRELESS, INC. , VANDERHELM, Ronald, John
发明人： VANDERHELM, Ronald, John
IPC分类号： H04L27/00
CPC分类号： H04B1/0003 , H04B1/3816 , H04B1/406 , H04L27/0008 , H04L2012/5616 , H04Q2213/199
摘要： A core wireless engine design includes the standardized CWE interface. The core wireless engine includes a transceiver, microprocessor and a standardized interface arrangement. The standardized interface arrangement is adapted to be connected to a variety of different host interfaces. This arrangement allows core wireless engines to be used with a variety of different host interfaces and form factors. In a preferred embodiment, the core wireless engine design is sized so that it can fit into a variety of form factor units.
摘要翻译：核心无线引擎设计包括标准化CWE接口。核心无线引擎包括收发器，微处理器和标准接口装置。标准化接口布置适于连接到各种不同的主机接口。这种安排允许核心无线引擎与各种不同的主机接口和外形因素一起使用。在优选实施例中，核心无线发动机设计的尺寸使得其可以适应各种形状因子单元。

3. 发明申请

WO2002060214A1 DATA UNIT HANDLING DEVICE AND METHOD OF CONTROLLING A DATA UNIT HANDLING DEVICE 审中-公开
标题翻译：数据单元处理装置和数据单元处理装置的控制方法
公开(公告)号：WO2002060214A1
公开(公告)日：2002-08-01
申请号：PCT/EP2002/000591
申请日：2002-01-22
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (publ) , MEYER, Michael , LUDWIG, Reiner
发明人： MEYER, Michael , LUDWIG, Reiner
IPC分类号： H04Q11/04
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5649 , H04L2012/5652 , H04L2012/5665 , H04L2012/5679
摘要： A data unit handling device and method of controlling a data unit handling device are described, where the implementation of a first protocol layer (1), when acting as a receiving peer in a communication, paces data units to be released from a buffer (31) to a second protocol layer (2) lying above the first protocol layer (1). The pacing is conducted over a release period T that is longer than the period of time that would occur if all of the data units of a given plurality were released instantly.
摘要翻译：描述了一种用于控制数据单元处理设备的数据单元处理设备和方法，其中第一协议层（1）的实现在作为通信中的接收对等体时，将从缓冲器（31）释放的数据单元）到位于第一协议层（1）上方的第二协议层（2）。如果给定的多个数据单元的所有数据单元立即被释放，则该发起时间段T超过发生的时间段。

4. 发明申请

WO02030148A1 ROUTER IN A PRIVATE ATM TERMINAL INSTALLATION 审中-公开
标题翻译：私人ATM终端安装中的路由器
公开(公告)号：WO02030148A1
公开(公告)日：2002-04-11
申请号：PCT/FR2001/003029
申请日：2001-10-01
IPC分类号： H04L12/70 , H04L12/935 , H04Q11/04
CPC分类号： H04L49/309 , H04L2012/5616 , H04L2012/562 , H04L2012/5685 , H04Q11/0478
摘要： In a terminal installation (1), a router (2) connects ATM access networks (RA1-RAM) to individual installations (4) of terminals (7), so as to route cells therebetween according to a routing table (25). The router also routes cells with routing addresses reserved for dialogue with a collective control unit (3) managing the routing table. The control unit processes said cells with reserved address to allocate internal logic channels to the dialogue between the latter and the terminals, and internal logic channels to incoming and outgoing communications with the terminals and internal communications between terminals, independently of the addressing plans of the access networks.
摘要翻译：在终端设备（1）中，路由器（2）将ATM接入网（RA1-RAM）连接到终端（7）的各个安装（4），以便根据路由表（25）在其间路由单元。路由器还通过路由地址路由小区，路由地址与管理路由表的集合控制单元（3）进行对话。控制单元用保留地址处理所述小区，以将内部逻辑信道分配给后者和终端之间的对话，以及内部逻辑信道，与终端进入和离开通信以及终端之间的内部通信，独立于接入寻址方案网络。

5. 发明申请

WO01095663A2 METHOD AND APPARATUS FOR CONTROLLING ATM STREAMS 审中-公开
标题翻译：控制ATM流的方法和装置
公开(公告)号：WO01095663A2
公开(公告)日：2001-12-13
申请号：PCT/US2001/017939
申请日：2001-06-04
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L12/56 , H04L2012/5616 , H04L2012/5681 , H04L2012/5682 , H04Q11/0478
摘要： The invention relates to a method and an apparatus for receiving and transmitting asynchronous transfer mode (ATM) cell streams over a bus. The invention provides a method for receiving ATM cells in a host from a client over a bus, comprising the steps of determining whether an ATM cell in a first storage device within the client is ready to be transferred over the bus to a second storage device within the host, preventing overflow of the second storage device by calculating a first available cell space in the second storage device as a function of a write value, a read value image and a size value of the second storage device, and transferring an ATM cell from the first storage device to the second storage device.
摘要翻译：本发明涉及一种通过总线接收和发送异步传输模式（ATM）信元流的方法和装置。本发明提供了一种用于通过总线从客户端接收主机中的ATM信元的方法，包括以下步骤：确定客户端内的第一存储设备中的ATM信元是否准备好通过总线传送到第二存储设备内主机，通过根据第二存储装置的写入值，读取值图像和大小值计算第二存储装置中的第一可用单元空间，防止第二存储装置的溢出，并且将ATM信元从第一存储设备到第二存储设备。

6. 发明申请

WO01008441A1 COMMUNICATION SYSTEM 审中-公开
标题翻译：通讯系统
公开(公告)号：WO01008441A1
公开(公告)日：2001-02-01
申请号：PCT/EP2000/006624
申请日：2000-07-12
IPC分类号： H04L12/70 , H04M1/00 , H04N7/14 , H04N7/173 , H04Q11/04
CPC分类号： H04N21/41407 , H04L2012/5616 , H04L2012/5664 , H04N7/17309 , H04N21/4333 , H04N21/4524 , H04N21/6181 , H04Q11/0478
摘要： In a communication system a communication device (2) is present for receiving a wideband broadcast signal from a head-end. For providing a return channel to enable interactive TV services, a GSM transceiver (34) is included in the communication device. In order to be able to provide also telephone services access control means (30) are present in the communication device (2) in order to control the access to the GSM transceiver without access conflicts causing an incorrect working system. The access control means switch between the return signals transmitted by a processor (12) and the telephone signals transmitted by a telephone terminal (22). In an embodiment of the invention, the communication device (2) is integrated in a TV set (3).
摘要翻译：在通信系统中，存在用于从头端接收宽带广播信号的通信设备（2）。为了提供返回信道以实现交互式电视服务，GSM收发器（34）被包括在通信设备中。为了能够提供电话服务，通信设备（2）中存在访问控制装置（30），以便控制对GSM收发信机的访问，而不会导致不正确的工作系统的访问冲突。访问控制装置在由处理器（12）发送的返回信号与由电话终端（22）发送的电话信号之间切换。在本发明的实施例中，通信设备（2）集成在电视机（3）中。

7. 发明申请

WO00052957A1 SYSTEM AND METHOD FOR MULTIPLE MODEM TRAFFIC REDIRECTION 审中-公开
标题翻译：用于多个调制解调器交通重定向的系统和方法
公开(公告)号：WO00052957A1
公开(公告)日：2000-09-08
申请号：PCT/US2000/005514
申请日：2000-03-02
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/5616 , H04L2012/5653
摘要： A communication system for communication of data packets associated with a packet switched network is disclosed herein. The system includes a port processor, a segmentation and reassembly device, and a host processor. The port processor communicates data packets to and from at least one communication device and at least one destination. The segmentation and reassembly device routes data packets to and from the port processor and the at least one destination. The host processor establishes a virtual circuit between the port processor and the segmentation and reassembly device. The host processor further directs the port processor to communicate data traffic to the segmentation and reassembly device via the virtual circuit, whereby the port processor and segmentation and reassembly device exchange data directly via the virtual circuit without per-packet handling by the host processor of all data traffic.
摘要翻译：本文公开了一种用于与分组交换网络相关联的数据分组的通信的通信系统。该系统包括端口处理器，分段和重组装置以及主处理器。端口处理器向至少一个通信设备和至少一个目的地传送数据分组。分段和重组装置将数据分组路由到端口处理器和至少一个目的地。主处理器在端口处理器和分段和重组装置之间建立虚拟电路。主机处理器还引导端口处理器经由虚拟电路将数据业务传送到分段和重组装置，由此端口处理器和分段和重新组装设备直接经由虚拟电路交换数据，而无需主机处理器的所有数据流量。

8. 发明申请

WO00048421A1 METHOD OF AND APPARATUS FOR ISOCHRONOUS DATA COMMUNICATION 审中-公开
标题翻译：用于异步数据通信的方法和装置
公开(公告)号：WO00048421A1
公开(公告)日：2000-08-17
申请号：PCT/EP2000/000512
申请日：2000-01-24
IPC分类号： H04N7/26 , H04J3/06 , H04L7/00 , H04L12/28 , H04L12/40 , H04L12/64 , H04L12/70 , H04M3/00 , H04Q11/04
CPC分类号： H04L12/40058 , H04J3/0632 , H04J3/0664 , H04L12/40071 , H04L2012/5616 , H04L2012/5649 , H04L2012/5664 , H04N21/4305 , H04N21/43632 , H04Q11/0478
摘要： In order to enable isochronous data to be transmitted over communications systems which may introduce timing jitter each packet of isochronous data is provided with a timestamp which indicates to a receiver the time at which a packet should be processed. The receiver notes the time the first packet of a data stream arrives and adds a given offset time which is greater than or equal to the maximum jitter to produce a time t1. Each succeeding packet is processed at a time t = t1 + (Tn-T1), where T1 is the timestamp in the first data packet and Tn is the timestamp in the current packet. Thus the processing at the receiver is dependent on the relative times of arrival of the packets rather than the absolute times defined by the timestamps.
摘要翻译：为了使同步数据能够通过可能引入定时抖动的通信系统传输，每个等时数据包都被提供有一个时间戳，该时间戳向接收者指示应该处理分组的时间。接收器注意到数据流的第一个数据包到达的时间，并添加了大于或等于最大抖动的给定偏移时间，以产生时间t1。每个后续分组在时间t = t1 +（Tn-T1）处理，其中T1是第一数据分组中的时间戳，Tn是当前分组中的时间戳。因此，接收机处理取决于分组的到达时间，而不是由时间戳定义的绝对时间。

9. 发明申请

WO0021327A3 METHOD FOR TRANSMITTING DIGITAL INFORMATION STRUCTURED IN BIT GROUPS ACCORDING TO A PROTOCOL DESIGNED FOR ANOTHER BIT GROUP STRUCTURE 审中-公开
标题翻译：用于传输数字METHOD IN比特组结构化的信息上的另一BITGRUPPENSTRUKTUR满载协议的基础
公开(公告)号：WO0021327A3
公开(公告)日：2000-07-06
申请号：PCT/DE9903171
申请日：1999-10-01
申请人： SIEMENS AG , WIENBOEKER JUERGEN , PAAR MICHAEL , VOGT GERHARD
发明人： WIENBOEKER JUERGEN , PAAR MICHAEL , VOGT GERHARD
IPC分类号： H04L12/70 , H04Q11/04
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5654 , H04L2012/5665 , H04L2012/5671
摘要： According to the inventive method, digital voice information (SP) which is compressed into first bit groups (QRT1-QRT94) comprising 2 bits by combining up to 2 first bit groups (QRT1-QRT94) each time with a second bit group (OCT7-OCT53) comprising 2 bits, whereby M is greater than N, is transmitted in ATM cells (AZ) or internet packets (IP) according to a protocol designed for the second bit groups (OCT7-OCT53). In doing this, the compressed voice information (SP) is efficiently transmitted also according to the protocol (AAL) designed for the bit groups comprising 2 bits.
摘要翻译：根据本发明的方法是数字的，在2 的压缩比特的语音信息（SP）的第一比特组（QRT1-QRT94）（由高达2的摘要第一比特组（QRT1-QRT94）向第二位组OCT7- ，2 位，其中M是大于N，按照一个（第二比特组辛烷-7- OCT53）设计的协议（AAL OCT53））（在ATM信元AZ）或因特网分组（IP）传输。使得压缩的话音信息被有效地（SP），并按照与设计用于位协议（AAL）2 的比特的组发送。

10. 发明申请

WO99039469A1 ATM SWITCH VOICE SERVER MODULE UTILIZING FLAG SIGNALLING 审中-公开
标题翻译： ATM开关语音服务器模块利用标志信号
公开(公告)号：WO99039469A1
公开(公告)日：1999-08-05
申请号：PCT/US1999/001227
申请日：1999-01-20
IPC分类号： H04L12/70 , H04L12/935 , H04Q11/04 , H04J3/22 , H04L12/56
CPC分类号： H04L49/3081 , H04L2012/5616 , H04L2012/5656 , H04L2012/5671 , H04Q11/0478
摘要： An ATM switch voice server module (18) has an interface (20) for receiving/multiplexing high adaptation layer (AAL) processor (40) which formats uncompressed data into AAL1 format and compressed data into AAL2 format, a management processor (50) which configures the interface (20) and the processors (30, 40), and preferably a data bus for carrying compressed voice data and a flag bus for carrying flags generated by the voice processor (30) relating to the voice data which are both coupled to the AAL processor (40), with the voice processor (30) ignoring all but the voice data portion of the data stream and the AAL processor (40) ignoring the voice data portion of the data stream. The voice processor (30) includes an array of digital signal processors (DSPs), including a plurality of rows and columns, with each row also including a field programmable gate array (FPGA).
摘要翻译： ATM交换机语音服务器模块（18）具有用于接收/复用高适应层（AAL）处理器（40）的接口（20），其将未压缩数据格式化为AAL1格式，将压缩数据格式化为AAL2格式，管理处理器（50）配置接口（20）和处理器（30,40），并且优选地用于承载压缩语音数据的数据总线和用于携带由语音处理器（30）产生的与语音数据有关的标志的标志总线，所述AAL处理器（40），其中所述语音处理器（30）忽略所述数据流的语音数据部分和忽略所述数据流的语音数据部分的所述AAL处理器（40）之外的所有其他所有数据。语音处理器（30）包括数字信号处理器（DSP）阵列，其包括多个行和列，每行还包括现场可编程门阵列（FPGA）。

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