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1. 发明申请

WO2018044519A1 APPARATUS AND METHOD FOR IN SITU ANALOG SIGNAL DIAGNOSTIC AND DEBUGGING WITH CALIBRATED ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：用于原位模拟信号诊断和调试以及校准的模拟数字转换器的设备和方法
公开(公告)号：WO2018044519A1
公开(公告)日：2018-03-08
申请号：PCT/US2017/046111
申请日：2017-08-09
申请人： QUALCOMM INCORPORATED
发明人： SONG, Deqiang , KONG, Xiaohua , PANDITA, Bupesh , GAO, Zhuo
IPC分类号： G01R31/316 , H03M1/10 , H03M1/12 , G01R31/3167
CPC分类号： H03M1/06 , G01R31/2884 , G01R31/3167 , H03M1/1009 , H03M1/12
摘要： An integrated circuit (IC) chip includes an on-chip analog signal monitoring circuit for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals into digital signals, storing the digital signals in an on-chip memory, and providing the digital signals to a test equipment upon request. The analog signal monitoring signal includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing a selected reference signal to an analog-to-digital converter (ADC) for calibration purpose and for routing a selected analog signal from one of the mixed signal cores to the ADC for digitizing purposes. The IC chip further includes an on-chip memory for storing the digitized analog signals for subsequent accessing by a test equipment for analysis. The IC chip includes a digital analog test point (ATP) for outputting the digitized analog signals.
摘要翻译：集成电路（IC）芯片包括片上模拟信号监视电路，用于监视由IC芯片内的一个或多个混合信号内核产生的一组模拟信号，将模拟信号转换为数字信号信号，将数字信号存储在片上存储器中，并根据请求将数字信号提供给测试设备。模拟信号监视信号包括用于产生精确电压和/或电流的片上参考发生器，用于将选定参考信号路由到模数转换器（ADC）以用于校准目的并用于路由选定模拟信号的开关网络信号从一个混合信号内核传送到ADC以进行数字化。 IC芯片还包括片上存储器，用于存储数字化模拟信号，以供测试设备随后访问以供分析。 IC芯片包括一个用于输出数字化模拟信号的数字模拟测试点（ATP）。

2. 发明申请

WO2018144207A1 CLOCK DATA RECOVERY WITH NON-UNIFORM CLOCK TRACKING 审中-公开
公开(公告)号：WO2018144207A1
公开(公告)日：2018-08-09
申请号：PCT/US2018/013636
申请日：2018-01-12
申请人： QUALCOMM INCORPORATED
发明人： SONG, Yu , ZHU, Zhi , LI, Miao , SUN, Li , SONG, Deqiang , CHANG, Chia Heng
IPC分类号： H04L7/00 , H03L7/081 , H04L7/033
摘要： Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

3. 发明申请

WO2018102076A1 CONTROLLER-PHY CONNECTION USING INTRA-CHIP SERDES 审中-公开
公开(公告)号：WO2018102076A1
公开(公告)日：2018-06-07
申请号：PCT/US2017/060031
申请日：2017-11-03
申请人： QUALCOMM INCORPORATED
发明人： KONG, Xiaohua , SONG, Deqiang , ZHU, Zhi , KWON, Ohjoon
IPC分类号： G06F3/14
摘要： An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual- protocol physical layer interface than the first controller.

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