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1. 发明申请

WO2008018033A3 SIGNAL PROCESSOR COMPRISING A FREQUENCY CONVERTER 审中-公开
标题翻译：包含频率转换器的信号处理器
公开(公告)号：WO2008018033A3
公开(公告)日：2008-04-03
申请号：PCT/IB2007053137
申请日：2007-08-08
申请人： NXP BV , VAN ZEIJL PAULUS T M , DE JONG GERBEN W , JEURISSEN DENNIS
发明人： VAN ZEIJL PAULUS T M , DE JONG GERBEN W , JEURISSEN DENNIS
IPC分类号： H03D7/14
CPC分类号： H03D7/166 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/165 , H03D2200/0025
摘要： A signal processor includes a frequency converter of the multiphase type. A first phase mixer (SWC1, TIS1) has a pair of switches (M11, M12). A second phase mixer (SWC2, TIS2) also has a pair of switches (M21, M22). The pair of switches of the first phase mixer and the pair of switches of the second phase mixer have a joint common switch node (CN1). A local oscillator generates an individual mixer driver signal (MD1+, MD1-, MDQ+, MDQ-) for each switch (M11, M12, M21, M22) in the aforementioned pairs. Each individual mixer driver signal comprises periodically occurring pulses, which are phase shifted with respect to the periodically occurring pulses in the other individual mixer driver signals. Preferably, there is substantially no overlap between the periodically occurring pulses in the individual mixer driver signals.
摘要翻译：信号处理器包括多相型变频器。第一相混频器（SWC1，TIS1）具有一对开关（M11，M12）。第二相混频器（SWC2，TIS2）也具有一对开关（M21，M22）。第一相混频器的一对开关和第二相混频器的一对开关具有联合公共开关节点（CN1）。本地振荡器在上述对中为每个开关（M11，M12，M21，M22）产生单独的混频器驱动器信号（MD1 +，MD1，MDQ +，MDQ-）。每个单独的混频器驱动器信号包括相对于其它单独混频器驱动器信号中周期性发生的脉冲相移的周期性发生的脉冲。优选地，各个混频器驱动器信号中周期性发生的脉冲之间基本上不存在重叠。

2. 发明申请

WO2009144642A3 LOW-1/F-NOISE LOCAL OSCILLATOR FOR NON-OVERLAPPING DIFFERENTIAL I/Q SIGNALS 审中-公开
标题翻译：用于非重叠差分I / Q信号的低1 / F噪声局部振荡器
公开(公告)号：WO2009144642A3
公开(公告)日：2010-01-21
申请号：PCT/IB2009052133
申请日：2009-05-21
申请人： NXP BV , DE JONG GERBEN W , JEURISSEN DENNIS
发明人： DE JONG GERBEN W , JEURISSEN DENNIS
IPC分类号： H03D7/16 , H03K5/156 , H03K17/28
CPC分类号： H03D7/166 , H03K5/1565 , H03K17/28
摘要： The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before- make (BBM) circuit ensures that the differential I/Q signals (LO_0, LO_90, LO_180, LO_270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-overlapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (?) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT_0, LT_90, LT_180, LT_270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (?) equal to zero. Thereby, the combined action of the BBM circuit and the feedback loops results in four non-overlapping differential I/Q signals (LO_0, LO_90, LO_180, LO_270) with constant and mutually equal duty cycles, and fixed and well-defined relative positions.
摘要翻译：本发明涉及如上所述的用于产生不重叠和免疫-1-f噪声信号的电路装置（300）。断开（BBM）电路确保驱动RF中的混频器（16A，16B）的晶体管（M11，M12，M21，M22）的差分I / Q信号（LO_0，LO_90，LO_180，LO_270）接收器（200）不重叠，以便随时只有这些晶体管中的一个导通。测量每个驱动信号的占空比，并且通过相应的差分放大器（38A-38D）确定与两个后续LO相位相对应的占空比中的差（α）。每个差分放大器被配置为具有电流输出（LT_0，LT_90，LT_180，LT_270），然后将其反馈到与第一LO相对应的输入缓冲器（30A-30D）的输入，以便调整其逻辑阈值（LT）电平，并使差值（？）等于零。因此，BBM电路和反馈环路的组合动作产生具有恒定且相互相等的占空比的四个不重叠的差分I / Q信号（LO_0，LO_90，LO_180，LO_270）以及固定且明确定义的相对位置。

3. 发明申请

WO2009057051A3 PASSIVE HARMONIC-REJECTION MIXER 审中-公开
标题翻译：被动谐波抑制混频器
公开(公告)号：WO2009057051A3
公开(公告)日：2010-04-15
申请号：PCT/IB2008054466
申请日：2008-10-29
申请人： NXP BV , BREKELMANS JOHANNES H A , DE JONG GERBEN W , EL WAFFAOUI RACHID , JEURISSEN DENNIS , VAN SINDEREN JAN , LEE SIMON WK
发明人： BREKELMANS JOHANNES H A , DE JONG GERBEN W , EL WAFFAOUI RACHID , JEURISSEN DENNIS , VAN SINDEREN JAN , LEE SIMON WK
IPC分类号： H03D7/16 , H03D7/18
CPC分类号： H03D7/165 , H03D7/18 , H03D2200/0082 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
摘要翻译：一种包括无源谐波抑制混频器的电子设备。无源谐波抑制混频器具有连接到几个子混频器级的输入，并且子混频器级连接到用于产生输出的求和模块。每个子混合级包括门控模块和相应的放大器，门控模块适于在控制信号的控制下选择性地传递具有反相极性的输入信号或输入信号。

4. 发明申请

WO2010125506A3 CALIBRATION OF PASSIVE HARMONIC-REJECTION MIXER 审中-公开
标题翻译：被动谐波抑制混合器的校准
公开(公告)号：WO2010125506A3
公开(公告)日：2011-07-21
申请号：PCT/IB2010051784
申请日：2010-04-23
申请人： NXP BV , JEURISSEN DENNIS , DE JONG GERBEN WILLEM , VAN SINDEREN JAN , BREKELMANS JOHANNES HUBERTUS ANTONIUS
发明人： JEURISSEN DENNIS , DE JONG GERBEN WILLEM , VAN SINDEREN JAN , BREKELMANS JOHANNES HUBERTUS ANTONIUS
IPC分类号： H03D7/14
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/1491
摘要： An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
摘要翻译：一种包括无源谐波抑制混频器（400）和校准电路（425）的电子设备。无源谐波抑制混频器具有连接到多个子混频器级（402）的输入（102），并且子混频器级连接到用于产生输出（104）的求和模块（406,408）。每个子混合级包括门控模块（414），放大器（416）和加权模块（418），门控模块在控制信号的控制下选择性地使输入信号或具有反相极性的输入信号。校准电路（425）适于将参考信号（430）输入到混频器的输入端，从混频器的输出接收输出信号（104），并设定权重（K1，K2，K3，K4）的加权模块以使输出信号匹配期望的输出信号。

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