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1. 发明申请

WO2008155301A3 DIRECT RF D-TO-A CONVERSION 审中-公开
标题翻译：直接RF D转换
公开(公告)号：WO2008155301A3
公开(公告)日：2009-02-19
申请号：PCT/EP2008057521
申请日：2008-06-16
申请人： ERICSSON TELEFON AB L M , DENT PAUL WILKINSON , KLEMMER NIKOLAUS
发明人： DENT PAUL WILKINSON , KLEMMER NIKOLAUS
IPC分类号： H03M1/66 , H03M3/00
CPC分类号： H03M1/662 , H03M3/41 , H03M3/502
摘要： A modulator described herein provides digital modulation and direct digital-to-analog conversion capable of achieving 12-bit resolution or higherfor high frequency signals. The modulator comprises a digital modulator, conversion circuit, and multiplexer. The digital modulator generates a plurality of sample streams at a plurality of different sample phases that collectively represent a desired modulated digital carrier waveform modulated by a digital input signal. The conversion circuit converts the sample streams into a plurality of continuous analog signals. The multiplexer multiplexes the analog signals together to generate a modulated analog carrier signal representative of the desired modulated digital carrier waveform.
摘要翻译：本文描述的调制器提供能够实现12位分辨率或更高的高频信号的数字调制和直接数模转换。调制器包括数字调制器，转换电路和多路复用器。数字调制器在多个不同的采样相位产生多个样本流，它们共同表示由数字输入信号调制的期望的调制数字载波波形。转换电路将采样流转换成多个连续的模拟信号。复用器将模拟信号复用在一起以产生表示所需调制数字载波波形的调制模拟载波信号。

2. 发明申请

WO2008077820A1 DIGITALLY CONTROLLED ANALOG FREQUENCY SYNTHESIZER 审中-公开
标题翻译：数字控制模拟频率合成器
公开(公告)号：WO2008077820A1
公开(公告)日：2008-07-03
申请号：PCT/EP2007/063961
申请日：2007-12-14
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) , WILKINSON DENT, Paul , KLEMMER, Nikolaus
发明人： WILKINSON DENT, Paul , KLEMMER, Nikolaus
IPC分类号： H03L7/085 , H03L7/18
CPC分类号： H03L7/091 , H03L7/087 , H03L7/093
摘要： A frequency synthesizer according to the present invention digitally controls an analog oscillator to generate an analog output signal at a desired frequency. A digitizing circuit converts a feedback signal derived from the oscillator output signal to a digitized multi-phase feedback signal. A comparator compares the digitized multi-phase feedback signal to a reference signal generated by the reference signal generator to generate an error signal indicative of the phase error in the output signal. A control circuit generates a control signal based on the error signal to control the frequency of the oscillator output signal.
摘要翻译：根据本发明的频率合成器数字地控制模拟振荡器以期望的频率产生模拟输出信号。数字化电路将从振荡器输出信号导出的反馈信号转换为数字化的多相反馈信号。比较器将数字化的多相反馈信号与由参考信号发生器产生的参考信号进行比较，以产生指示输出信号中的相位误差的误差信号。控制电路根据误差信号产生控制信号，以控制振荡器输出信号的频率。

3. 发明申请

WO2004027979A1 INTEGRATED, DIGITALLY-CONTROLLED CRYSTAL OSCILLATOR 审中-公开
标题翻译：集成的数字控制晶体振荡器
公开(公告)号：WO2004027979A1
公开(公告)日：2004-04-01
申请号：PCT/US2003/026453
申请日：2003-08-22
申请人： ERICSSON INC. , DENT, Paul , KLEMMER, Nikolaus
发明人： DENT, Paul , KLEMMER, Nikolaus
IPC分类号： H03B5/32
CPC分类号： H03B5/366 , H03B5/32
摘要： A quartz crystal oscillator comprises a balanced circuit with a quartz crystal resonator device connected in series resonance across a balanced, low impedance node within a sustaining amplifier. A phase modulator such as a quadrature modulator is included in the feedback loop to allow programming of the loop phase shift thereby to alter the frequency point on the crystal resonance curve at which the circuit oscillates. The in phase loop signal is hardlimited while the quadrature loop signal component is not hardlimited with the effect that the frequency control curve slope is more accurately defined. An active neutralization of the crystal's parasitic shunt capacitance is disclosed for obtaining a linear frequency control curve.
摘要翻译：石英晶体振荡器包括具有石英晶体谐振器装置的平衡电路，其在保持放大器内的平衡，低阻抗节点上串联谐振连接。在反馈回路中包括诸如正交调制器的相位调制器，以允许编程环路相移，从而改变电路振荡的晶体谐振曲线上的频率点。同相环路信号是硬限制的，而正交环路信号分量不受硬限制，具有更准确地定义频率控制曲线斜率的效果。公开了用于获得线性频率控制曲线的晶体寄生并联电容的主动中和。

4. 发明申请

WO2006045346A1 FRACTIONAL FREQUENCY SYNTHESIZER 审中-公开
标题翻译：部分频率合成器
公开(公告)号：WO2006045346A1
公开(公告)日：2006-05-04
申请号：PCT/EP2005/001616
申请日：2005-02-17
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ) , KLEMMER, Nikolaus
发明人： KLEMMER, Nikolaus
IPC分类号： H03L7/16
CPC分类号： H03L7/0996 , H03L7/083 , H03L7/16
摘要： A frequency synthesizer circuit generates an output clock signal having a desired frequency relationship with an input reference signal, and offers essentially arbitrary relational values and adjustment resolution within any applicable circuit limits. The frequency synthesizer includes a ring oscillator circuit (12) that provides multiple phases of its output clock signal, a phase selection circuit (18) to select a phase of the output clock signal for feedback to an oscillator control circuit (16) at each cycle of the reference signal according to a phase selection sequence. The oscillator control circuit generates a control signal responsive to comparing the selected phases of the output clock signal with the reference signal, and the phase selection circuit may include a modulator (34) to generate phase selection sequences having desired time-average values that enable arbitrary frequency adjustability.
摘要翻译：频率合成器电路产生与输入参考信号具有期望频率关系的输出时钟信号，并且在任何适用的电路限制内提供基本上任意的关系值和调整分辨率。频率合成器包括提供其输出时钟信号的多个相位的环形振荡器电路（12），相位选择电路（18），用于在每个周期选择用于反馈到振荡器控制电路（16）的输出时钟信号的相位的参考信号。振荡器控制电路响应于将输出时钟信号的所选相位与参考信号进行比较而产生控制信号，并且相位选择电路可以包括调制器（34），以产生具有期望的时间平均值的相位选择序列，频率可调性。

5. 发明申请

WO2006029754A1 DELAY CALIBRATION IN POLAR MODULATION TRANSMITTERS 审中-公开
标题翻译：极性调制变送器的延迟校准
公开(公告)号：WO2006029754A1
公开(公告)日：2006-03-23
申请号：PCT/EP2005/009659
申请日：2005-09-08
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , KLEMMER, Nikolaus
发明人： KLEMMER, Nikolaus
IPC分类号： H04L27/36
CPC分类号： H04L27/361 , H04L7/0041 , H04L7/0337
摘要： A method and apparatus for dynamically compensating for delay mismatch between a supply signal and an input signal of a power amplifier in polar modulation transmitters. One exemplary polar modulation transmitter according to the present invention comprises a power amplifier, a phase modulator, a regulator, a delay tracking circuit, and a delay circuit. The phase modulator derives the amplifier-input signal responsive to one or more phase signals, while the regulator derives the amplifier supply signal responsive to an amplitude signal. Based on the amplitude signal and the amplifier supply signal, the delay tracking circuit tracks an observed amplitude path delay. The delay circuit adjusts a path delay associated with the phase signal, responsive to the observed amplitude path delay, to compensate for the delay mismatch.
摘要翻译：一种用于动态地补偿极性调制发射机中的功率放大器的电源信号和输入信号之间的延迟失配的方法和装置。根据本发明的一个示例性极性调制发射机包括功率放大器，相位调制器，调节器，延迟跟踪电路和延迟电路。响应于一个或多个相位信号，相位调制器导出放大器输入信号，而稳压器响应幅度信号导出放大器电源信号。基于振幅信号和放大器电源信号，延迟跟踪电路跟踪观察到的振幅路径延迟。延迟电路响应于观察到的幅度路径延迟来调整与相位信号相关联的路径延迟，以补偿延迟失配。

6. 发明申请

WO2011076541A1 DELAY, GAIN AND PHASE ESTIMATION FOR MEASUREMENT RECEIVERS 审中-公开
标题翻译：测量接收机的延迟，增益和相位估计
公开(公告)号：WO2011076541A1
公开(公告)日：2011-06-30
申请号：PCT/EP2010/068812
申请日：2010-12-03
申请人： ST-ERICSSON SA , KLEMMER, Nikolaus , AL-QAQ, Wael , ZHANG, Zhihang
发明人： KLEMMER, Nikolaus , AL-QAQ, Wael , ZHANG, Zhihang
IPC分类号： H04B17/00
CPC分类号： H04B17/10
摘要： Phase and gain of a transmit signal are measured at a transmitter by determining a first time delay having a first resolution at a measurement receiver between a reference signal from which the transmit signal is generated and a measured signal derived from the transmit signal by comparing amplitudes of the reference signal and the measured signal. A second time delay having a second resolution finer than the first resolution is determined at the measurement receiver between the reference signal and the measured signal based on the first time delay. The reference signal and the measured signal are time aligned at the measurement receiver based on the second time delay and the phase and gain of the transmit signal are estimated after the reference signal and the measured signal are time aligned.
摘要翻译：发射信号的相位和增益通过在测量接收机处确定具有第一分辨率的第一时间延迟来测量，所述第一时间延迟在产生发射信号的参考信号与从发射信号导出的测量信号之间进行比较，参考信号和测量信号。基于第一时间延迟，在参考信号和测量信号之间的测量接收器处确定具有比第一分辨率更精细的第二分辨率的第二时间延迟。参考信号和测量信号基于第二时间延迟在测量接收机处进行时间对准，并且在参考信号和测量信号被时间对准之后估计发射信号的相位和增益。

7. 发明申请

WO2009043757A1 APPARATUS AND METHODS FOR FREQUENCY CONTROL IN A MULTI-OUTPUT FREQUENCY SYNTHESIZER 审中-公开
标题翻译：多输出频率合成器中频率控制的装置和方法
公开(公告)号：WO2009043757A1
公开(公告)日：2009-04-09
申请号：PCT/EP2008/062638
申请日：2008-09-22
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , NILSSON, Magnus , KLEMMER, Nikolaus , PETTY, John Stewart , UPPATHIL, Satish
发明人： NILSSON, Magnus , KLEMMER, Nikolaus , PETTY, John Stewart , UPPATHIL, Satish
IPC分类号： H03J7/06 , H04B1/38 , H03L7/23 , G01S1/00
CPC分类号： H03L7/23 , G01S19/235 , H03L7/1976
摘要： Methods and circuits for synthesizing two or more signals phase-locked to a common reference frequency signal are disclosed. In one embodiment, a method comprises generating first and second output signals (350, 370) phase-locked to a reference clock signal, using first and second phase- locked loop circuits (200', 200' '). In response to a detected frequency error in the first output signal, the first output signal (350) is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal (370) is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another exemplary method, first and second output signals are generated as described above, using first and second phase-locked loop circuits. The first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit and generating a control signal (360) to adjust the frequency of the reference clock signal, in response to detected frequency error in the first output signal. Because the second output signal (370) is derived from the common reference clock signal, adjustments to the reference clock frequency (FREF) will also adjust the frequency of the second output signal. Additional adjustments to the second output signal (370) may be applied in some embodiments by adjusting a frequency-division ratio in the second phase-locked loop circuits. Circuits for implementing the described methods are also disclosed.
摘要翻译：公开了用于合成两个或更多个锁相到公共参考频率信号的信号的方法和电路。在一个实施例中，一种方法包括使用第一和第二锁相环电路（200'，200“）产生锁相到参考时钟信号的第一和第二输出信号（350,370）。响应于第一输出信号中的检测到的频率误差，通过调整第一锁相环电路中的分频比来校正第一输出信号（350）。通过使用从检测到的频率误差计算出的调整参数，通过调整第二锁相环电路中的分频比来对与第一输出信号的校正分开地校正第二输出信号（370）。在另一示例性方法中，使用第一和第二锁相环电路如上所述地生成第一和第二输出信号。响应于第一输出信号中检测到的频率误差，通过调节第一锁相环电路中的分频比并产生控制信号（360）来校正参考时钟信号的频率来校正第一输出信号。由于第二输出信号（370）是从公共参考时钟信号导出的，对基准时钟频率（FREF）的调整也将调整第二输出信号的频率。在一些实施例中，可以通过调整第二锁相环电路中的分频比来对第二输出信号（370）进行额外的调整。还公开了用于实现所述方法的电路。

8. 发明申请

WO2008155301A2 DIRECT RF D-TO-A CONVERSION 审中-公开
标题翻译：直接RF D转换
公开(公告)号：WO2008155301A2
公开(公告)日：2008-12-24
申请号：PCT/EP2008/057521
申请日：2008-06-16
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , DENT, Paul Wilkinson , KLEMMER, Nikolaus
发明人： DENT, Paul Wilkinson , KLEMMER, Nikolaus
IPC分类号： H03M1/66 , H03M3/00
CPC分类号： H03M1/662 , H03M3/41 , H03M3/502
摘要： A modulator described herein provides digital modulation and direct digital-to-analog conversion capable of achieving 12-bit resolution or higherfor high frequency signals. The modulator comprises a digital modulator, conversion circuit, and multiplexer. The digital modulator generates a plurality of sample streams at a plurality of different sample phases that collectively represent a desired modulated digital carrier waveform modulated by a digital input signal. The conversion circuit converts the sample streams into a plurality of continuous analog signals. The multiplexer multiplexes the analog signals together to generate a modulated analog carrier signal representative of the desired modulated digital carrier waveform.
摘要翻译：本文所述的调制器提供能够实现12位分辨率或更高的高频信号的数字调制和直接数模转换。调制器包括数字调制器，转换电路和多路复用器。数字调制器在多个不同的采样相位产生多个样本流，它们共同表示由数字输入信号调制的期望的调制数字载波波形。转换电路将采样流转换为多个连续的模拟信号。多路复用器将模拟信号复用在一起以产生表示所需调制数字载波波形的调制模拟载波信号。

9. 发明申请

WO2011064122A1 A PHASE LOCKED LOOP FREQUENCY SYNTHESIZER CIRCUIT WITH IMPROVED NOISE PERFORMANCE 审中-公开
标题翻译：具有改进噪声性能的相位锁定环路频率合成器电路
公开(公告)号：WO2011064122A1
公开(公告)日：2011-06-03
申请号：PCT/EP2010/067557
申请日：2010-11-16
申请人： ST-ERICSSON SA , NILSSON, Magnus , KLEMMER, Nikolaus
发明人： NILSSON, Magnus , KLEMMER, Nikolaus
IPC分类号： H03L7/197 , H03L7/089
CPC分类号： H03L7/1976 , H03L7/0891 , H03L7/0895
摘要： A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector signals (UP/DN) dependent on the sign of the phase difference; and a charge pump (61) comprising current generating means and controlled switches (64, 65) arranged to convert pulses on the detector signals to current pulses from a reference voltage (Vdd') to a common terminal (Vloop) connected to the loop filter or to current pulses from the common terminal to ground. The current generating means comprises at least one resistor (62, 63) connected between the common terminal and the switches, and the charge pump comprises an operational amplifier (66) coupled to keep the reference voltage at twice the voltage at the common terminal.
摘要翻译：锁相环频率合成器包括压控振荡器; 用于向振荡器提供控制电压的环路滤波器; 相位频率检测器，被配置为检测参考信号和从振荡器信号产生的反馈信号之间的相位差，并根据相位差的符号在检测器信号（UP / DN）上产生脉冲; 以及电荷泵（61），包括电流产生装置和受控开关（64,65），其被布置成将检测器信号上的脉冲转换成从参考电压（Vdd'）到连接到环路滤波器的公共端子（V loop）的电流脉冲或从公共端到地的电流脉冲。电流产生装置包括连接在公共端子和开关之间的至少一个电阻器（62,63），并且电荷泵包括耦合以将参考电压保持在公共端子处的电压的两倍的运算放大器（66）。

10. 发明申请

WO2009040329A1 SINGLE MULTI-MODE CLOCK SOURCE FOR WIRELESS DEVICES 审中-公开
标题翻译：用于无线设备的单模时钟源
公开(公告)号：WO2009040329A1
公开(公告)日：2009-04-02
申请号：PCT/EP2008/062625
申请日：2008-09-22
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (publ) , PETTY, John Stewart , UPPATHIL, Satish , KLEMMER, Nikolaus
发明人： PETTY, John Stewart , UPPATHIL, Satish , KLEMMER, Nikolaus
IPC分类号： H04B1/16
CPC分类号： H04W52/029 , Y02D70/00 , Y02D70/1222 , Y02D70/142 , Y02D70/144 , Y02D70/164
摘要： The wireless device described herein uses a sing le crystal oscillator to generate the high and low frequency clock signals required by the wireless device during both active and inactive radio communications. An exemplary multi-mode clock unit comprises a single crystal oscillator operable in a normal power mode and a reduced power mode, and a control unit that selectively switches the crystal oscillator between the first and second power modes based on a current clock signal quality requirement. The control unit may selectively switch between the first and second power modes by selectively varying a capacitive load of the crystal oscillator and/or by varying a drive signal of the crystal oscillator. For example, the control unit may select the normal power mode when a cellular transceiver is active, and a reduced power mode when the cellular transceiver is inactive to reduce power consumption during the inactive state.
摘要翻译：本文描述的无线设备使用单晶振荡器来在有源和无源无线电通信期间产生无线设备所需的高和低频时钟信号。示例性的多模式时钟单元包括以正常功率模式和降低功率模式操作的单晶振荡器，以及控制单元，其基于当前时钟信号质量要求在第一和第二功率模式之间选择性地切换晶体振荡器。控制单元可以通过选择性地改变晶体振荡器的容性负载和/或通过改变晶体振荡器的驱动信号来选择性地在第一和第二功率模式之间切换。例如，当蜂窝收发器处于活动状态时，控制单元可以选择正常功率模式，并且当蜂窝收发器不活动时降低功率模式以在非活动状态期间降低功耗。

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