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1. 发明公开

US20230274750A1 MULTI-MODE CHANNEL CODING 审中-公开
公开(公告)号：US20230274750A1
公开(公告)日：2023-08-31
申请号：US18312853
申请日：2023-05-05
申请人： Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
发明人： Jan BUETHE , Conrad BENNDORF , Manfred LUTZKY , Markus SCHNELL , Maximilian SCHLEGEL
IPC分类号： G10L19/035 , H04B17/309 , G10L21/0324 , G10L19/022 , H03M13/07 , H03M13/15 , H04L1/00
CPC分类号： G10L19/035 , H04B17/309 , G10L21/0324 , G10L19/022 , H03M13/07 , H03M13/1515 , H04L1/0009 , H04L1/0032 , H04L1/0046 , H04L1/0042 , H04L1/0045 , H04L1/0084
摘要： A channel encoder for encoding a frame includes a multi-mode redundancy encoder for redundancy encoding the frame in accordance with a certain coding mode from a set of different coding modes, wherein the coding modes are different from each other with respect to an amount of redundancy added to the frame, wherein the multi-mode redundancy encoder is configured to output a coded frame including at least one code word; and a colorator for applying a coloration sequence to the at least one code word; wherein the coloration sequence is such that at least one bit of the code word is changed by the application of the at least one of coloration sequence, wherein the specific coloration sequence is selected in accordance with the certain coding mode.

2. 发明申请

US20210375295A1 AUDIO TRANSMITTER PROCESSOR, AUDIO RECEIVER PROCESSOR AND RELATED METHODS AND COMPUTER PROGRAMS 有权
公开(公告)号：US20210375295A1
公开(公告)日：2021-12-02
申请号：US17400422
申请日：2021-08-12
申请人： Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
发明人： Adrian TOMASEK , Ralph SPERSCHNEIDER , Jan BÜTHE , Alexander TSCHEKALINSKIJ , Manfred LUTZKY
IPC分类号： G10L19/022 , H03M13/15 , H03M13/07
摘要： An audio transmitter processor for generating an error protected frame using encoded audio data of an audio frame, the encoded audio data for the audio frame having a first amount of information units and a second amount of information units, has: a frame builder for building a codeword frame having a codeword raster, wherein the frame builder is configured to determine a border between a first amount of information units and a second amount of information units so that a starting information unit of the second amount of information units coincides with a codeword border; and an error protection coder to obtain a plurality of processed codewords representing the error protected frame.

3. 发明授权

US10595051B2 Picture coding apparatus that codes on a macroblock basis by performing a signal conversion process 有权
公开(公告)号：US10595051B2
公开(公告)日：2020-03-17
申请号：US16448381
申请日：2019-06-21
申请人： Panasonic Intellectual Property Corporation of America
发明人： Shinya Kadono , Makoto Hagai
IPC分类号： H04N19/91 , H03M7/40 , H03M7/42 , H03M13/07 , H03M13/35 , H04N21/61 , H04N19/70 , H04N19/172 , H04N19/46 , H04N19/13 , H04N19/61 , H04N19/103 , H04N19/146 , H04N19/157 , H04N19/174 , H04N19/132 , H04L29/06 , H04N19/176 , H04N19/184
摘要： A frame coding unit generates individual picture signal information from a moving picture signal, and outputs a frame code value which is a numeric value to be obtained as a result of coding picture signal information of each frame. A variable length coding unit decomposes the frame code value into unit frame code values which are basic units of coding, converts the unit frame code values into frame code words using only a single code table, and constructs a frame stream by combining the converted frame code words. A multiplexing unit multiplexes a header stream which is constructed through a method equivalent to a conventional method and the frame stream, and constructs a picture coded signal.

4. 发明授权

US10382058B2 Fast update of data packet checksums 有权
公开(公告)号：US10382058B2
公开(公告)日：2019-08-13
申请号：US15640787
申请日：2017-07-03
申请人： DELL PRODUCTS LP
发明人： George Weigt
IPC分类号： H03M13/09 , G06F11/10 , H04L1/00 , H03M13/07 , H04L29/06
摘要： A device includes a processor and a checksum module, wherein the checksum module calculates, for first data, an updated checksum that complies with Internet Engineering Task Force Request For Comments Number 1624 using twos-complement arithmetic. The processor replaces the original checksum with the updated checksum to update a data packet.

5. 发明授权

US10236913B2 Error checking and correcting decoder 有权
公开(公告)号：US10236913B2
公开(公告)日：2019-03-19
申请号：US15592220
申请日：2017-05-11
申请人： Winbond Electronics Corp.
发明人： Chuen-Der Lien , Ngatik Cheung
IPC分类号： H03M13/15 , H03M13/07 , H03M13/00
摘要： An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.

6. 发明申请

US20180278273A1 DECODING DEVICE AND DECODING METHOD 审中-公开
公开(公告)号：US20180278273A1
公开(公告)日：2018-09-27
申请号：US15702204
申请日：2017-09-12
申请人： Toshiba Memory Corporation
发明人： Naoko KIFUNE , Hironori UCHIKAWA , Daiki WATANABE
IPC分类号： H03M13/29 , H03M13/07 , H03M13/11 , G06F11/10 , G11C29/52
CPC分类号： H03M13/2927 , G06F11/1012 , G06F11/1068 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , H03M13/07 , H03M13/1108 , H03M13/1515 , H03M13/152 , H03M13/2909 , H03M13/2948
摘要： According to one embodiment, a decoding device that decodes a multi-dimensional error correction code having two or more component codes includes a storage unit that stores therein the multi-dimensional error correction code, an additional-information storage unit that manages each syndrome of the at least two component codes or a reliability flag indicating whether the syndrome has a value of 0 or other than 0, a decoder that performs a first decoding process in a unit of component code with respect to the multi-dimensional error correction code stored in the storage unit to detect an error vector of each component code, and a detection unit that determines whether detection of the error vector by the decoder is false detection, based on the syndrome or the reliability flag stored in the additional-information storage unit.

7. 发明授权

US09698825B2 Fast update of data packet checksums 有权
公开(公告)号：US09698825B2
公开(公告)日：2017-07-04
申请号：US14521035
申请日：2014-10-22
申请人： Dell Products, LP
发明人： George Weigt
IPC分类号： H03M13/09 , G06F11/10 , H04L1/00 , H03M13/07 , H04L29/06
CPC分类号： H03M13/096 , G06F11/1004 , H03M13/07 , H03M13/093 , H04L1/0061 , H04L1/0072 , H04L1/0083 , H04L69/16 , H04L69/161
摘要： A device includes a processor and a checksum module, wherein the checksum module calculates, for first data, an updated checksum that complies with Internet Engineering Task Force Request For Comments Number 1624 using twos-complement arithmetic. The processor replaces the original checksum with the updated checksum to update a data packet.

8. 发明授权

US09384083B2 Error location search circuit, and error check and correction circuit and memory device including the same 有权
标题翻译：错误位置搜索电路，以及错误检查和校正电路和包含相同的存储器件
公开(公告)号：US09384083B2
公开(公告)日：2016-07-05
申请号：US14034803
申请日：2013-09-24
申请人： Samsung Electronics Co., Ltd.
发明人： Daisuke Fujiwara , Makoto Hirano
IPC分类号： H03M13/00 , G06F11/10 , H03M13/07 , H03M13/15
CPC分类号： G06F11/10 , H03M13/07 , H03M13/1545 , H03M13/158 , H03M13/6561
摘要： Provided is an error check and correction (ECC) circuit which includes a Chien search unit configured to determine whether there is an error in a data string. The Chien search unit includes a circuit configured to calculate a first bit string by multiplying a plurality of elements of Galois Field GF(2n) and a value of (n-k)-bit, and calculate a second bit string by multiplying the plurality of elements and a value of k-bit; and a plurality of Chien search circuits configured to combine the first bit string and the second bit string to calculate the arbitrary element. The plurality of Chien search circuits are arranged in a matrix along a row direction and a column direction. The first bit string is provided in the row direction or the column direction, and the second bit string is provided in a direction different from the direction of the first bit string.
摘要翻译：提供了一种错误检查和校正（ECC）电路，其包括被配置为确定数据串中是否存在错误的Chien搜索单元。 Chien搜索单元包括被配置为通过乘以伽罗瓦域GF（2n）的多个元素和（nk）比特的值来计算第一比特串的电路，并且通过将多个元素相乘来计算第二比特串， k位的值; 以及多个Chien搜索电路，被配置为组合第一位串和第二位串以计算任意元素。多个Chien搜索电路沿着行方向和列方向排列成矩阵。第一位串被设置在行方向或列方向上，并且第二位串被设置在与第一位串的方向不同的方向上。

9. 发明授权

US08984380B2 Method and system for operating a communication circuit configurable to support one or more data rates 有权
标题翻译：用于操作可配置为支持一个或多个数据速率的通信电路的方法和系统
公开(公告)号：US08984380B2
公开(公告)日：2015-03-17
申请号：US13733798
申请日：2013-01-03
申请人： ALTERA Corporation
发明人： Divya Vijayaraghavan , Chong H. Lee , Keith Duwel , Vinson Chan
IPC分类号： H03M13/00 , H03M13/35 , H03M13/37 , H04L12/931 , H03M13/07
CPC分类号： H03M13/353 , H03M13/07 , H03M13/3738 , H03M13/63 , H03M13/6511 , H03M13/6516 , H03M13/6519 , H04L49/604
摘要： A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module.
摘要翻译：一种用于操作可配置为在单个设备上支持一个或多个通信标准的通信电路的方法和系统。通信电路包括：发送装置，其包括以第一数据速率操作的PCS模块和以第二数据速率操作的第二PCS模块。电路还包括多个前向纠错（FEC）编码和解码模块，每个以指定的数据速率运行。第一组FEC编码和解码模块被配置为支持第一PCS模块，并且第二组FEC编码和解码模块被配置为支持第二PCS模块。

10. 发明申请

US20140108895A1 ERROR CORRECTION CODE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：错误校正代码电路和包括其的存储器件
公开(公告)号：US20140108895A1
公开(公告)日：2014-04-17
申请号：US14054190
申请日：2013-10-15
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Daisuke FUJIWARA
IPC分类号： H03M13/07
CPC分类号： H03M13/1545 , G06F11/08 , G06F11/10 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G11C29/04 , H03M13/1148 , H03M13/151 , H03M13/1515 , H03M13/152 , H03M13/153 , H03M13/154 , H03M13/1575 , H03M13/158 , H03M13/19 , H03M13/3707 , H03M13/6566
摘要： The ECC circuit includes a Chien search unit configured to determine whether there is an error in each bit of a data sequence. The Chien search unit selects a coefficient of a nonlinear term from among terms of an error locator polynomial as a nonlinear coefficient, separates the error locator polynomial into a first location equation including only linear terms and a second location equation including only nonlinear terms, determines a third location equation by dividing the first location equation by the nonlinear coefficient, determines a fourth location equation by dividing the second location equation by the nonlinear coefficient, and determines whether there is an error for each of the bits by performing an XOR operation on a result of the third location equation using the substitution value and a result of the fourth location equation using an arbitrary element of the error locator polynomial as a substitution value.
摘要翻译： ECC电路包括被配置为确定数据序列的每个比特是否存在错误的Chien搜索单元。 Chien搜索单元从误差定位多项式的项中选择非线性项的系数作为非线性系数，将误差定位多项式分离为仅包括线性项的第一位置方程和仅包括非线性项的第二位置方程，确定通过将第一位置方程除以非线性系数的第三位置方程通过将第二位置方程除以非线性系数来确定第四位置方程，并且通过对结果执行异或运算来确定是否存在针对每个位的错误使用替代值的第三位置方程和使用误差定位多项式的任意元素作为替代值的第四位置方程的结果。

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