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1. 发明申请

US20090083506A1 Method and system for memory thermal load sharing using memory on die termination 有权
标题翻译：使用存储器进行存储器热负载共享的方法和系统
公开(公告)号：US20090083506A1
公开(公告)日：2009-03-26
申请号：US12005968
申请日：2007-12-28
申请人： David G. Reed , Brad W. Simeral , Roman Surgutchik , Joshua Titus
发明人： David G. Reed , Brad W. Simeral , Roman Surgutchik , Joshua Titus
IPC分类号： G06F12/16 , G11C99/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1057 , G11C7/1078 , G11C7/109
摘要： Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory components to avoid imposing a thermal load from the ODT cycle on a second of the memory components.
摘要翻译：内存组件温度信息用于实现用于ODT（终端）热负载管理的方法。访问多个存储器组件的相应温度，并且基于该温度，ODT周期针对第一存储器组件以避免在第二存储器组件上施加来自ODT周期的热负载。

2. 发明授权

US10346088B2 Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND 有权
公开(公告)号：US10346088B2
公开(公告)日：2019-07-09
申请号：US15721674
申请日：2017-09-29
申请人： Intel Corporation
发明人： Niccolo Righetti , Akira Goda , Violante Moschiano , Christian Caillat , Giuseppina Puzzilli
IPC分类号： G06F3/06 , G11C11/56 , H01L27/11524 , G11C99/00
摘要： In one embodiment, an apparatus comprises a controller to determine an erase state of a first memory deck independently from an erase state of a second memory deck, the first memory deck comprising a first plurality of wordlines and a first channel, the first memory deck comprising a first plurality of memory cells that are each coupled to the first channel and a respective one of the first plurality of wordlines; the second memory deck comprising a second plurality of wordlines and a second channel, the second channel coupled to the first channel, the second memory deck comprising a second plurality of memory cells that are each coupled to the second channel and a respective one of the second plurality of wordlines; and determine an erase state of the second memory deck independently from an erase state of the first memory deck.

3. 发明授权

US09006003B1 Method of detecting bitmap failure associated with physical coordinate 有权
标题翻译：检测与物理坐标相关的位图故障的方法
公开(公告)号：US09006003B1
公开(公告)日：2015-04-14
申请号：US14220993
申请日：2014-03-20
申请人： MACRONIX International Co., Ltd.
发明人： Tuung Luoh , Chi-Min Chen , Ling-Wuu Yang , Ta-Hone Yang , Kuang-Chao Chen
IPC分类号： H01L21/00 , G11C99/00 , H01L21/66 , G01R31/28
CPC分类号： H01L22/14 , G01R31/2851 , G06T7/0004 , G06T2207/10061 , G06T2207/30148 , G11C29/006 , G11C29/56008 , G11C2029/5604
摘要： A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in each of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a bitmap failure detection is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted into a plurality of physical locations, and the physical locations are overlapped with the physical coordinates so as to rapidly obtain correlations between the failure bits and the defects.
摘要翻译：提供了一种检测与物理坐标相关联的位图故障的方法。在该方法中，首先获得晶片映射检查的数据，并且数据包括晶片内的每个层中的缺陷图像和缺陷的多个物理坐标。此后，执行位图故障检测以获得晶片内的故障位的数字坐标。数字坐标被转换成多个物理位置，并且物理位置与物理坐标重叠，以便快速获得故障位与缺陷之间的相关性。

4. 发明申请

US20110254885A1 DATA RECORDING METHOD FOR LONG-TERM READING OF SAID DATA 审中-公开
标题翻译：用于长时间读取数据的数据记录方法
公开(公告)号：US20110254885A1
公开(公告)日：2011-10-20
申请号：US12742027
申请日：2008-11-10
申请人： Thierry Prigent , Eric Prigent , Karine Van Heumen
发明人： Thierry Prigent , Eric Prigent , Karine Van Heumen
IPC分类号： G11C99/00
CPC分类号： G11B23/38
摘要： According to this method, there is recorded on the same recording medium (1): a) an encoded recording (A) of the data allowing them to be read automatically, b) a recording (B), intended for intuitive visual reading, of the knowledge necessary for using means for decoding (MD) the data in order to read them automatically.
摘要翻译：根据该方法，记录在相同的记录介质（1）上：a）允许自动读取的数据的编码记录（A），b）用于直观视觉读取的记录（B）使用用于解码（MD）数据的手段以便自动读取它们所需的知识。

5. 发明申请

US20150262718A1 STORAGE SYSTEM FOR PHARMACY 审中-公开
标题翻译：药物储存系统
公开(公告)号：US20150262718A1
公开(公告)日：2015-09-17
申请号：US14727584
申请日：2015-06-01
申请人： GSL Solutions, Inc.
发明人： Shelton Louie , Stephen A. Garrett
IPC分类号： G11C99/00
CPC分类号： G11C99/00 , A61J1/16 , G07F11/64 , Y10T29/49002 , Y10T29/49069
摘要： A storage system for a pharmacy that has a frame containing a frame with a plurality of storage carriers detachably suspended therefrom. The carriers are sized to receive filled prescription orders and the like and include individual identifiers that facilitate locating the carriers at a specific location on the frame. Preferably, the storage system includes a tracking system that detects, monitors, and displays to a worker the location of the storage carrier containing a particular customer's prescription order, thereby providing easy retrieval of the customer's prescription order.
摘要翻译：一种用于药房的存储系统，其具有包含具有可拆卸地从其悬挂的多个存储载体的框架的框架。载体的大小适于接收填充的处方订单等，并且包括有助于将载体定位在框架上的特定位置的各个标识符。优选地，存储系统包括跟踪系统，其向工作者检测，监视和显示包含特定客户的处方订单的存储载体的位置，从而提供对客户处方订单的容易检索。

6. 发明申请

US20110032770A1 High Temperature Methods for Enhancing Retention Characteristics of Memory Devices 有权
标题翻译：高温方法提高存储器件的保留特性
公开(公告)号：US20110032770A1
公开(公告)日：2011-02-10
申请号：US12911264
申请日：2010-10-25
申请人： Chao-I Wu , Tzu Hsuan Hsu
发明人： Chao-I Wu , Tzu Hsuan Hsu
IPC分类号： G11C16/34 , G11C99/00
CPC分类号： H01L21/324 , G11C16/04 , G11C16/3454 , G11C29/06 , G11C29/50 , G11C29/50016 , H01L29/66833
摘要： Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the memory device that checks the logic state of memory cells, and a reprogramming process to program the memory device once again by programming memory cells in a 0-state to a high-Vt state. The baking step of placing the memory device in a high temperature environment causes a charge loss by expelling shallow trapped charges, resulting in the improvement of retention reliability.
摘要翻译：描述了通过执行保持改进程序来改善存储器件的保持性的方法。保持改善过程包括在高温环境中的存储器件的烘烤过程，检查存储器单元的逻辑状态的存储器件的校验过程以及重新编程过程，以通过将存储器单元中的程序 0状态到高Vt状态。将存储器件放置在高温环境中的烘烤步骤通过排出浅的被捕获的电荷导致电荷损失，导致保持可靠性的提高。

7. 发明申请

US20110002175A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20110002175A1
公开(公告)日：2011-01-06
申请号：US12613914
申请日：2009-11-06
申请人： Tae-Sig Chang
发明人： Tae-Sig Chang
IPC分类号： G11C99/00 , G11C7/10
CPC分类号： G11C7/04 , G11C17/18 , G11C29/785
摘要： A semiconductor memory device includes: a repair node; a fuse one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse; and a voltage drop unit coupled between the pull-up unit and the fuse and configured to lower a voltage level of the driving voltage.
摘要翻译：半导体存储器件包括：修复节点; 保险丝的一侧耦合到修复节点; 配置成有选择地将接地电压传送到所述修复节点的下拉单元; 上拉单元，被配置为选择性地将驱动电压传送到所述保险丝的另一侧; 以及耦合在所述上拉单元和所述保险丝之间并被配置为降低所述驱动电压的电压电平的电压降单元。

8. 发明申请

US20190102104A1 METHOD AND APPARATUS FOR PER-DECK ERASE VERIFY AND DYNAMIC INHIBIT IN 3D NAND 审中-公开
公开(公告)号：US20190102104A1
公开(公告)日：2019-04-04
申请号：US15721674
申请日：2017-09-29
申请人： Intel Corporation
发明人： Niccolo Righetti , Akira Goda , Violante Moschiano , Christian Caillat , Giuseppina Puzzilli
IPC分类号： G06F3/06 , G11C11/56 , G11C99/00 , H01L27/11524
CPC分类号： G06F3/0653 , G06F3/0602 , G11C11/5635 , G11C99/00 , H01L27/11524 , H01L27/11582
摘要： In one embodiment, an apparatus comprises a controller to determine an erase state of a first memory deck independently from an erase state of a second memory deck, the first memory deck comprising a first plurality of wordlines and a first channel, the first memory deck comprising a first plurality of memory cells that are each coupled to the first channel and a respective one of the first plurality of wordlines; the second memory deck comprising a second plurality of wordlines and a second channel, the second channel coupled to the first channel, the second memory deck comprising a second plurality of memory cells that are each coupled to the second channel and a respective one of the second plurality of wordlines; and determine an erase state of the second memory deck independently from an erase state of the first memory deck.

9. 发明授权

US09047992B2 Suspended storage system for pharmacy 有权
标题翻译：药房暂停存储系统
公开(公告)号：US09047992B2
公开(公告)日：2015-06-02
申请号：US13931012
申请日：2013-06-28
申请人： GSL Solutions, Inc.
发明人： Shelton Louie , Stephen A. Garrett
IPC分类号： A47G29/00 , G11C99/00 , A61J1/16 , G07F11/64
CPC分类号： G11C99/00 , A61J1/16 , G07F11/64 , Y10T29/49002 , Y10T29/49069
摘要： A storage system for a pharmacy that has a frame containing a rack-like structure with a plurality of storage carriers detachably suspended therefrom. The carriers are sized to receive filled prescription orders and the like and include individual identifiers that facilitate locating the carriers at a specific location on the rack-like structure. Preferably, the storage system includes a tracking system that detects, monitors, and displays to a worker the location of the storage carrier containing a particular customer's prescription order, thereby providing easy retrieval of the customer's prescription order.
摘要翻译：一种用于药房的存储系统，其具有包含具有可拆卸地从其悬挂的多个存储载体的齿条状结构的框架。载体的尺寸适于接收填充的处方订单等，并且包括有助于将载体定位在架状结构上的特定位置处的各个标识符。优选地，存储系统包括跟踪系统，其向工作者检测，监视和显示包含特定客户的处方订单的存储载体的位置，从而提供对客户处方订单的容易检索。

10. 发明申请

US20130315016A1 COLUMN REPAIR CIRCUIT 有权
标题翻译：柱修理电路
公开(公告)号：US20130315016A1
公开(公告)日：2013-11-28
申请号：US13585169
申请日：2012-08-14
申请人： Nak Kyu PARK
发明人： Nak Kyu PARK
IPC分类号： G11C99/00
CPC分类号： G11C29/808 , G11C17/16 , G11C17/18 , G11C29/787
摘要： A column repair circuit of a semiconductor memory apparatus includes a plurality of mats and performs a column repair operation to replace failed cells among a plurality of memory cells provided in the mats. The column repair circuit includes two or more fuse units configured to perform the column repair operation. Each of the fuse units includes a plurality of fuses, and is configured in such a manner that m mats correspond to one fuse or n mats correspond to one fuse, where m and n are natural numbers equal to or more than 1 and different from each other.
摘要翻译：半导体存储装置的列修复电路包括多个垫，并执行列修复操作以替换设置在垫中的多个存储单元中的故障单元。列修复电路包括被配置为执行列修复操作的两个或更多熔丝单元。每个保险丝单元包括多个保险丝，并且以这样的方式配置：m个垫对应于一个保险丝或n个垫对应于一个保险丝，其中m和n是等于或大于1的自然数并且与每个不同其他。

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