专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11275909B1 Current-mode analog multiply-accumulate circuits for artificial intelligence 有权
公开(公告)号：US11275909B1
公开(公告)日：2022-03-15
申请号：US16730539
申请日：2019-12-30
申请人： Ali Tasdighi Far
发明人： Ali Tasdighi Far
IPC分类号： G06G7/163 , G06G7/164 , G06N3/063 , G05F3/26 , H03F3/45 , H03G1/00 , H03M1/74 , H03M1/12
摘要： Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

2. 发明申请

US20190272395A1 SINGLE TRANSISTOR MULTIPLIER AND METHOD THEREFOR 审中-公开
公开(公告)号：US20190272395A1
公开(公告)日：2019-09-05
申请号：US16291311
申请日：2019-03-04
申请人： DAVID SCHIE , SERGEY GAITUKEVICH , PETER DRABOS , ANDREAS SIBRAI , ERIK SIBRAI
发明人： DAVID SCHIE , SERGEY GAITUKEVICH , PETER DRABOS , ANDREAS SIBRAI , ERIK SIBRAI
IPC分类号： G06G7/164 , G06N3/02 , H03F3/45
摘要： A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents. In a next reset phase, the second capacitor holds a multiplied value of charge.

3. 发明申请

US20050173767A1 Multiplier 失效
标题翻译：乘数
公开(公告)号：US20050173767A1
公开(公告)日：2005-08-11
申请号：US10499867
申请日：2002-11-29
申请人： Atsushi Hirabayashi , Kenji Komori
发明人： Atsushi Hirabayashi , Kenji Komori
IPC分类号： G06G7/12 , G06G7/16 , G06G7/163 , G06G7/164 , H03F3/45 , H01L29/76
CPC分类号： G06G7/164
摘要： A conventional multiplier which uses a MOS transistor has a subject that, in order to compensate for a variation of a bias voltage or the like, it is necessary to add a complicated correcting circuit to an outputting section or the like, and the circuit scale becomes great and the power consumption increases. A multiplier includes NMOS transistors (3, 4, 5) and constant voltage sources (6, 9, 12) connected to the gates of the NMOS transistors (3, 4, 5), respectively, and the voltage value of a constant voltage source (9) and the voltage value of another constant voltage source (12) are set equal to each other. Further, the NMOS transistor (4) and the NMOS transistor (5) are formed same as each other.
摘要翻译：使用MOS晶体管的常规乘法器的主题是为了补偿偏置电压等的变化，需要向输出部等添加复杂的校正电路，并且电路规模变为大功率消耗增加。乘法器包括分别连接到NMOS晶体管（3,4,5）的栅极的NMOS晶体管（3,4,5）和恒定电压源（6,9,12），并且恒定电压源的电压值（9），另一个恒定电压源（12）的电压值彼此相等。此外，NMOS晶体管（4）和NMOS晶体管（5）形成为彼此相同。

4. 发明授权

US5909136A Quarter-square multiplier based on the dynamic bias current technique 失效
标题翻译：基于动态偏置电流技术的四分之一平方乘法器
公开(公告)号：US5909136A
公开(公告)日：1999-06-01
申请号：US928452
申请日：1997-09-12
申请人： Katsuji Kimura
发明人： Katsuji Kimura
IPC分类号： G06G7/16 , G06G7/163 , G06G7/164 , H03F3/45
CPC分类号： G06G7/164 , H03F3/45085 , H03F3/45183 , H03F3/4521 , H03F2203/45112 , H03F2203/45366 , H03F2203/45454 , H03F2203/45466 , H03F2203/45471 , H03F2203/45574 , H03F2203/45656
摘要： A four-quadrant multiplier which is constructed from two squaring circuits using the quarter-square technique and is suitable for an integrated circuit (IC) or a large-scale integrated circuit (LSI). Each of the squaring circuits has a pair of differential input terminals, an output terminal and two differential pairs. Each of differential pairs is composed of first and second transistors whose sources or emitters are connected in common, receives a differential input voltage impressed between the differential input terminals. In each differential pair, a constant current source of a predetermined current value and an dynamic bias current source are inserted in parallel between the common sources or the common emitters and the grounding point. The dynamic bias current source is realized by a current mirror circuit which outputs current equal to the drain current or the collector current of the second transistor. Therefore, the tail current of each differential pair is current given by the sum of the output current of the second transistor and the predetermined constant current. The output current of each squaring circuit is represented by the sum of the drain currents or the collector currents of the second transistors of both of the differential pairs.
摘要翻译：一个四象限乘法器，它由使用四分之一平方法的两个平方电路构成，适用于集成电路（IC）或大规模集成电路（LSI）。每个平方电路具有一对差分输入端子，输出端子和两个差分对。每个差分对由其源极或发射极共同连接的第一和第二晶体管组成，接收在差分输入端子之间施加的差分输入电压。在每个差分对中，将预定电流值的恒定电流源和动态偏置电流源并联插入到公共源或公共发射器和接地点之间。动态偏置电流源由电流镜电路实现，电流镜电路输出等于第二晶体管的漏极电流或集电极电流的电流。因此，每个差分对的尾电流是由第二晶体管的输出电流和预定恒定电流之和给出的电流。每个平方电路的输出电流由两个差分对的第二晶体管的漏极电流或集电极电流之和表示。

5. 发明授权

US5617052A Transconductance-variable analog multiplier using triple-tail cells 失效
标题翻译：使用三尾电池的跨导可变模拟乘法器
公开(公告)号：US5617052A
公开(公告)日：1997-04-01
申请号：US629132
申请日：1996-04-08
申请人： Katsuji Kimura
发明人： Katsuji Kimura
IPC分类号： G06G7/163 , G06G7/164 , G06F7/44
CPC分类号： G06G7/164
摘要： An analog multiplier realizing drastically enlarged input voltage ranges with good linearity, low-voltage operation, and transconductance characteristics adjustment. This multiplier contains a first squarer applied differentially with first and second input signals in opposite phases, and a second squarer applied differentially with said first and second input signals in the same phase. Each of squarers is realized by a bipolar or MOS triple-tail cell including first, second and third transistors whose emitter or sources are coupled together and driven by a single tail current. Bases or gates of the first and second transistors form input ends of the squarer. Collectors or drains of the first and second transistors are coupled together to form one of output ends of the squarer. A collector or drain of the third transistor form the other thereof. A base or gate of the third transistor forms an input end to be applied with a bias signal. The transconductance varies dependent upon the applied bias voltage.
摘要翻译：模拟乘法器实现了大幅度输入电压范围，具有良好的线性度，低电压工作和跨导特性调整。该乘法器包括与相位相位中的第一和第二输入信号差分地施加的第一平方器，并且在相同相位中与所述第一和第二输入信号差分地施加第二平方器。每个平方器由双极或MOS三尾单元实现，其包括第一，第二和第三晶体管，其发射极或源极耦合在一起并由单尾电流驱动。第一和第二晶体管的基极或栅极形成平方的输入端。第一和第二晶体管的集电极或漏极耦合在一起以形成平方的输出端之一。第三晶体管的集电极或漏极构成另一晶体管的另一晶体管。第三晶体管的基极或栅极形成要施加偏置信号的输入端。跨导根据施加的偏置电压而变化。

6. 发明授权

US5557228A Four-quadrant multiplier 失效
标题翻译：四象限乘数
公开(公告)号：US5557228A
公开(公告)日：1996-09-17
申请号：US506914
申请日：1995-07-26
申请人： Shen-Iuan Liu
发明人： Shen-Iuan Liu
IPC分类号： G06G7/164 , H03B19/14 , H03C1/54 , H03B19/00
CPC分类号： G06G7/164 , H03B19/14 , H03C1/542
摘要： A four-quadrant multiplier using BiCMOS circuits can be applied in high-frequency analog circuits. The four-quadrant multiplier includes two transform circuits to generate two intermediate signals proportional to the first and second input signals, respectively; four square circuits to provide a squaring relationship between current and voltage in the four square circuits; and two resistors serving as a load for the currents of the four square means and for outputting the resultant voltage to an output port.
摘要翻译：使用BiCMOS电路的四象限乘法器可以应用于高频模拟电路。四象限乘法器包括两个变换电路，分别产生与第一和第二输入信号成比例的两个中间信号; 四个方形电路在四个方形电路中提供电流和电压之间的平方关系; 和两个电阻器，用作四个方形装置的电流的负载，并将合成的电压输出到输出端口。

7. 发明授权

US3253135A Quarter square analog multiplier 失效
标题翻译：四分之一平方的模拟乘数
公开(公告)号：US3253135A
公开(公告)日：1966-05-24
申请号：US17443862
申请日：1962-02-20
申请人： SYSTRON DONNER CORP
发明人： COLLINGS JERRY M , SANSUM VICTOR H
IPC分类号： G06G7/164
CPC分类号： G06G7/164

8. 发明授权

US3000565A Circuits for obtaining four quadrant analogue multiplication 失效
标题翻译：用于获得四象限模拟乘法的电路
公开(公告)号：US3000565A
公开(公告)日：1961-09-19
申请号：US65207457
申请日：1957-04-10
申请人： WILKINSON ROBERT H
发明人： WILKINSON ROBERT H
IPC分类号： G06G7/164
CPC分类号： G06G7/164

9. 发明授权

US2959350A Computer multiplier circuit 失效
标题翻译：电脑乘法电路
公开(公告)号：US2959350A
公开(公告)日：1960-11-08
申请号：US59125156
申请日：1956-06-13
申请人： TRUEBLOOD RICHARD D
发明人： TRUEBLOOD RICHARD D
IPC分类号： G06G7/164
CPC分类号： G06G7/164

10. 发明授权

US2945626A Quarter-square multiplier 失效
标题翻译：四分之一平方乘数
公开(公告)号：US2945626A
公开(公告)日：1960-07-19
申请号：US14103750
申请日：1950-01-28
申请人： VANCE ARTHUR W , GOLDBERG EDWIN A
发明人： VANCE ARTHUR W , GOLDBERG EDWIN A
IPC分类号： G06G7/164
CPC分类号： G06G7/164

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式