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1. 发明公开

US20240394204A1 PROCESSING METHOD AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20240394204A1
公开(公告)日：2024-11-28
申请号：US18639192
申请日：2024-04-18
申请人： Lenovo (Beijing) Limited
发明人： Dong LI
IPC分类号： G06F13/22
CPC分类号： G06F13/22 , G06F2213/40
摘要： A processing method includes obtaining an interface use status of a first module and controlling a status identifier of a first storage area to correspond to the interface use status. The first module is electrically connected to another module via an interface. The status identifier is used to support detecting a status of the first module.

2. 发明公开

US20240264871A1 STORAGE TRANSACTIONS WITH PREDICTABLE LATENCY 审中-公开
公开(公告)号：US20240264871A1
公开(公告)日：2024-08-08
申请号：US18618912
申请日：2024-03-27
申请人： Intel Corporation
发明人： Ziye YANG , James R. HARRIS , Kiran PATIL , Benjamin WALKER , Sudheer MOGILAPPAGARI , Yadong LI , Mark WUNDERLICH , Anil VASUDEVAN
IPC分类号： G06F9/50 , G06F9/46 , G06F9/54 , G06F13/22 , H04L67/1097 , H04L69/16
CPC分类号： G06F9/5027 , G06F9/466 , G06F9/546 , G06F13/22 , H04L67/1097 , H04L69/16
摘要： The disclosure concerns at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers. The disclosure concerns at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.

3. 发明公开

US20240134808A1 POLLING SCHEME WITH PRIORITY IN AN INDUSTRIAL NETWORK SYSTEM 审中-公开
公开(公告)号：US20240134808A1
公开(公告)日：2024-04-25
申请号：US18378846
申请日：2023-10-10
申请人： Schneider Electric Industries SAS
发明人： Bertrand Fruchard , Caijin Wang
IPC分类号： G06F13/26 , G06F13/22
CPC分类号： G06F13/26 , G06F13/225
摘要： For polling communication devices in a communication system including a host device and communication devices. The host device is connected to the communication devices via a clock line for transmitting a clock signal to the communication devices and via an arbitration line implemented with “OR” logic for receiving arbitration signal transmitted by the communication devices. Each communication device is configured to pull up or down the arbitration line for sending an arbitration signal when the communication device is ready to send data to the host device. Each communication device is configured to pull down the arbitration line for sending an arbitration signal when the communication device has no data to send to the host device. The host device (HD) is able to: send a clock signal on the clock line during an arbitration cycle, causing the communication devices to send respective arbitration signals towards the arbitration line, during the arbitration cycle, receive a final signal corresponding to an addition of the arbitration signals, during the arbitration cycle, resulting from the “OR” logic applied to the arbitration signals, detect the communication devices ready to send data based on the “1” bit of the final signal, select, among the detected communication devices, the communication device associated with the highest priority in a priority table containing the priorities associated with the communication devices, and poll the selected communication device to receive data from the selected communication device during a communication cycle.

4. 发明公开

US20240012772A1 HIGH PERFORMANCE INTERCONNECT 审中-公开
公开(公告)号：US20240012772A1
公开(公告)日：2024-01-11
申请号：US18347236
申请日：2023-07-05
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808
CPC分类号： G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/4286 , G06F8/71 , G06F8/77 , G06F9/30145 , G06F13/4221 , G06F12/0806 , G06F12/0833 , G06F9/466 , G06F13/4022 , G06F9/44505 , G06F13/4282 , G06F1/3287 , G06F13/4068 , G06F11/1004 , G06F13/4291 , H04L9/0662 , G06F12/0808 , H04L45/74
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

5. 发明授权

US11809348B2 Digital bus activity monitor 有权
公开(公告)号：US11809348B2
公开(公告)日：2023-11-07
申请号：US17888687
申请日：2022-08-16
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Gary Franklin Chard , Tpinn Ronnie Koh , Harshil Atulkumar Shah
IPC分类号： G06F13/14 , G06F13/38 , G06F13/40 , G06F13/42 , G06F13/22 , G06F1/3225
CPC分类号： G06F13/22 , G06F1/3225 , G06F13/404 , G06F13/4282 , G06F13/4291 , G06F2213/0016
摘要： One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

6. 发明授权

US11561913B2 Processing input data at different clock frequencies based on a number of polls of an I/O range for an application detecting input data 有权
公开(公告)号：US11561913B2
公开(公告)日：2023-01-24
申请号：US17485808
申请日：2021-09-27
申请人： Nasdaq Technology AB
发明人： Hakan Winbom
IPC分类号： G06F13/22 , G06F1/3209 , G06F1/3234 , G06F1/324 , H04L12/64 , G06F1/08
摘要： Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected.

7. 发明申请

US20220414035A1 ADAPTIVE HYBRID POLLING BASED ON OUTSTANDING INPUT/OUTPUT (I/O) DETERMINATION 有权
公开(公告)号：US20220414035A1
公开(公告)日：2022-12-29
申请号：US17402652
申请日：2021-08-16
申请人： VMware, Inc.
发明人： Yang BAI , Wenchao CUI , Haitao GUO , Ran PENG , Tianji ZHAO
IPC分类号： G06F13/22 , G06F13/24 , G06F9/455 , G06F9/38
摘要： An adaptive hybrid polling technique combines an interrupt mode with a polling mode, and is based on outstanding input/output (OIO) determination to improve I/O performance and to save processor cycles. The OIO includes two types of I/O commands: (1) I/O commands submitted to storage devices for processing, and (2) I/O commands completed by the storage devices but not yet acknowledged by host software. The adaptive hybrid polling technique involves two phases to determine when to poll based on current OIO commands. In the first phase, a determination is made whether there is an adequate number of the first type of OIO commands to prepare for polling. In the second phase, a determination is made whether there is an adequate number of the second type of OIS commands to activate polling.

8. 发明申请

US20220374366A1 EFFICIENT RETRIEVAL OF SENSOR DATA WHILE ENSURING ATOMICITY 有权
公开(公告)号：US20220374366A1
公开(公告)日：2022-11-24
申请号：US17325095
申请日：2021-05-19
申请人： Pony AI Inc.
发明人： Pingfan Meng , Stephen Lee
IPC分类号： G06F12/1009 , G06F12/1027 , G06F12/02 , G06F13/22 , G01S17/86
摘要： A computing device performs initial processing of sensor data. The computing device performs obtaining sensor data, writing the sensor data to first addresses of a dynamically allocated buffer associated with the computing device, encoding the sensor data, writing the encoded sensor data to second addresses of the dynamically allocated buffer, in response to completing the writing of the encoded sensor data, indicating that the writing of the encoded sensor data has been completed, receiving, from a computing resource, a polling request to read the encoded sensor data, transmitting, to the computing resource, a status that the writing of the encoded sensor data to the second addresses has been completed, reading, to a memory of the computing resource, the encoded sensor data, receiving, from the computing resource, a second status that the encoded sensor data has been read, and removing, from the dynamically allocated buffer, the encoded sensor data.

9. 发明授权

US11347663B2 Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing 有权
公开(公告)号：US11347663B2
公开(公告)日：2022-05-31
申请号：US17081483
申请日：2020-10-27
申请人： Micron Technology, Inc.
发明人： Luigi Pilolli
IPC分类号： G06F13/16 , G06F13/40 , G06F13/28 , G06F13/22
摘要： A set of memory commands associated with one or more memory dies of a memory device are communicated via a first portion of an interface to the memory device. Communication of a set of data bursts corresponding to the set of memory commands to the one or more memory dies via a second portion of the interface is caused, wherein one or more of the set of memory commands is communicated via the first interface concurrently with one or more of the set of data bursts.

10. 发明申请

US20220164302A1 ADAPTIVE I/O COMPLETION METHOD AND RECORDABLE MEDIUM STORING PROGRAM FOR THE SAME 有权
公开(公告)号：US20220164302A1
公开(公告)日：2022-05-26
申请号：US17535894
申请日：2021-11-26
申请人： Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
发明人： Young Ik EOM , Jong Gyu PARK , Kwon Je OH
IPC分类号： G06F13/22 , G06F9/48
摘要： In accordance with an aspect of the present disclosure, there is provided a method for adaptive I/O completion. The method comprises, determining whether an application is a foreground application or a background application; in response to the application determined to be the foreground application, determining whether the application is a CPU-bound application or an I/O-bound application; and applying an I/O polling method in response to that the application determined to be the foreground application and the I/O-bound application, and applying an interrupt method in response to that the application determined to be the foreground application and the CPU-bound application, or the application determined to be the background application.

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