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1. 发明授权

US12055584B2 Systems, methods, and devices for high-speed input/output margin testing 有权
公开(公告)号：US12055584B2
公开(公告)日：2024-08-06
申请号：US17534409
申请日：2021-11-23
申请人： Tektronix, Inc.
发明人： Daniel S. Froelich , Sam J. Strickling
IPC分类号： G01R31/3183 , G01R31/30 , G01R31/317 , G01R31/3181 , G01R31/3185 , G06F30/367 , G06F115/12 , G06F119/06 , G06F119/12
CPC分类号： G01R31/31707 , G01R31/30 , G01R31/31813 , G01R31/318314 , G01R31/318385 , G01R31/318572 , G06F30/367 , G06F2115/12 , G06F2119/06 , G06F2119/12
摘要： A margin testing device includes at least one interface structured to connect to a device under test (DUT) one or more controllers structured to create a set of test signals based on a sequence of pseudo random data and one or more pre-defined parameters, and an output structured to send the set of test signals to the DUT. Methods and a system for testing a DUT with the disclosed margin tester and other testing device are also described.

2. 发明公开

US20240118340A1 PROCESSOR TEST PATTERN GENERATION AND APPLICATION FOR TESTER SYSTEMS 审中-公开
公开(公告)号：US20240118340A1
公开(公告)日：2024-04-11
申请号：US18230003
申请日：2023-08-03
申请人： ADVANTEST CORPORATION
发明人： Edmundo De La Puente , Mei-Mei Su , Srdjan Malisic
IPC分类号： G01R31/3181 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/31813 , G01R31/31724 , G01R31/318544
摘要： A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation. The test system also includes a low power module coupled to and external to the high performance processor, the low power module capable of operating in at least one low power mode, the high performance processor for directing the low power module to configure the plurality of DUTs into at least one low power mode and further for testing the plurality of DUTs using commands and data in low power. The test system further includes driver hardware for applying the commands and data in low power to the plurality of DUTs which are configured for low power operation during the testing.

3. 发明授权

US11927627B2 Systems, methods, and devices for high-speed input/output margin testing 有权
公开(公告)号：US11927627B2
公开(公告)日：2024-03-12
申请号：US17534404
申请日：2021-11-23
申请人： Tektronix, Inc.
发明人： Daniel S. Froelich , Sam J. Strickling
IPC分类号： G06F30/367 , G01R31/30 , G01R31/317 , G01R31/3181 , G01R31/3183 , G01R31/3185 , G06F115/12 , G06F119/06 , G06F119/12
CPC分类号： G01R31/31707 , G01R31/30 , G01R31/31813 , G01R31/318314 , G01R31/318385 , G01R31/318572 , G06F30/367 , G06F2115/12 , G06F2119/06 , G06F2119/12
摘要： A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.

4. 发明授权

US11694010B2 Reformatting scan patterns in presence of hold type pipelines 有权
公开(公告)号：US11694010B2
公开(公告)日：2023-07-04
申请号：US17518024
申请日：2021-11-03
申请人： Synopsys, Inc.
发明人： Amit Gopal M. Purohit , Sorin Ioan Popa , Denis Martin , Paras Chhabra
IPC分类号： G06F30/30 , G06F30/333 , G01R31/317 , G01R31/3177 , G01R31/3181 , G01R31/319 , G01R31/3183 , G01R31/3185
CPC分类号： G06F30/333 , G01R31/3177 , G01R31/31704 , G01R31/31813 , G01R31/31908 , G01R31/318371 , G01R31/318583
摘要： A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.

5. 发明申请

US20230055833A1 PARAMETER SETTING METHOD AND APPARATUS, SYSTEM, AND STORAGE MEDIUM 有权
公开(公告)号：US20230055833A1
公开(公告)日：2023-02-23
申请号：US17442263
申请日：2021-06-17
申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.
发明人： Hao He
IPC分类号： G01R31/3181 , G01R31/28 , G01R31/3183
摘要： The present application provides a parameter setting method and apparatus, a system, and a storage medium. The parameter setting method includes: obtaining first setting values of multiple memory parameters and storage locations of the multiple memory parameters in a non-volatile memory; generating a first parameter setting instruction according to the first setting value and the storage location of each memory parameter; and sending the first parameter setting instruction to a test device, so that the test device sets the memory parameter stored at the storage location in the non-volatile memory as the first setting value.

6. 发明申请

US20220413036A1 VIRTUAL QUALITY CONTROL INTERPOLATION AND PROCESS FEEDBACK IN THE PRODUCTION OF MEMORY DEVICES 有权
公开(公告)号：US20220413036A1
公开(公告)日：2022-12-29
申请号：US17360573
申请日：2021-06-28
申请人： SanDisk Technologies LLC
发明人： Yusuke Ikawa , Tsuyoshi Sendoda , Kei Samura , Masaaki Higashitani
IPC分类号： G01R31/27 , G01R31/3183 , G01R31/317 , G01R31/3181 , G06N3/063
摘要： To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

7. 发明授权

US11320487B1 Programmable test compactor for improving defect determination 有权
公开(公告)号：US11320487B1
公开(公告)日：2022-05-03
申请号：US17330515
申请日：2021-05-26
申请人： Siemens Industry Software Inc.
发明人： Wu-Tung Cheng , Chen Wang , Mark A. Kassab
IPC分类号： G01R31/3185 , G01R31/317 , G01R31/3183 , G01R31/3181
摘要： A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; a test response compactor configured to compact the test responses; and shuffler circuitry inserted between outputs of the scan chains and inputs of the test response compactor, the shuffler circuitry comprising state elements configured to delay output signals from some of the scan chains for one or more clock cycles based on a control signal, the control signal varying with the test patterns.

8. 发明授权

US11295831B2 Systems and methods to detect cell-internal defects 有权
公开(公告)号：US11295831B2
公开(公告)日：2022-04-05
申请号：US16912156
申请日：2020-06-25
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ankita Patidar , Sandeep Kumar Goel
IPC分类号： G01R31/3183 , G11C29/44 , G11C29/12 , G11C29/10 , G11C29/02 , G11C29/50 , G01R31/3185 , G06F11/07 , G01R31/28 , G01R31/3181
摘要： A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.

9. 发明授权

US11156662B2 Software defined LFSR for LOC delay testing low-power test compression 有权
公开(公告)号：US11156662B2
公开(公告)日：2021-10-26
申请号：US16351386
申请日：2019-03-12
申请人： Tsinghua University
发明人： Dong Xiang
IPC分类号： G01R31/28 , G06F11/00 , G01R31/3183 , G01R31/3181 , G01R31/3185 , G01R31/3187
摘要： A software-defined linear feedback shift register (SLFSR) implements a low-power test compression for launch-on-capture (LOC). Each bit of an extra register controls a stage of the SLFSR. A control vector is shifted into the extra register to indicate whether a primitive polynomial contains the stage of the non-zero bit. Therefore, SLFSR can configure any primitive polynomials with different degrees by loading different control vectors without any hardware overhead. A low-power test compression method and design for testability (DFT) architecture provide LOC transition fault testing by using seed encoding scheme, low-power test application procedure and a software-defined linear-feedback shift-register (SLFSR) architecture. The seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set.

10. 发明授权

US11092646B1 Determining a voltage and/or frequency for a performance mode 有权
公开(公告)号：US11092646B1
公开(公告)日：2021-08-17
申请号：US16794105
申请日：2020-02-18
申请人： QUALCOMM Incorporated
发明人： Sonia Ghosh , Changho Jung , Chulmin Jung
IPC分类号： G01R31/3181 , G01R31/317 , G01J1/18
摘要： According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.

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