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1. 发明授权

US4573178A Counter employing feedback shift register controlling hysteresis circuit 失效
标题翻译：计数器采用反馈移位寄存器控制迟滞电路
公开(公告)号：US4573178A
公开(公告)日：1986-02-25
申请号：US756566
申请日：1985-07-18
申请人： Hiroshi Morito
发明人： Hiroshi Morito
IPC分类号： H03K27/00 , H03K3/2893 , H03K3/3565 , H03K3/84 , H03K23/54 , H03K25/12
CPC分类号： H03K3/3565 , H03K23/54 , H03K3/2893 , H03K3/84
摘要： A counter for counting pulses or dividing frequencies has a timing signal generator circuit for generating a timing signal at a predetermined interval. A hysteresis circuit has input-output characteristics defining a low input threshold level and a high input threshold level. A control circuit responds to the timing signal for generating at least three control signals having different levels including a first control signal having a level lower than the low input threshold level, a second control signal having a level higher than the high input threshold level, and a third control signal having an intermediate level which is between the low input threshold level and the high input threshold level. The counter has a very large capacity, simple construction, and is effective with both analog and digital signals.
摘要翻译：用于计数脉冲或分频的计数器具有用于以预定间隔产生定时信号的定时信号发生器电路。滞后电路具有定义低输入阈值电平和高输入阈值电平的输入 - 输出特性。控制电路响应于定时信号，用于产生具有不同电平的至少三个控制信号，包括具有低于低输入阈值电平的电平的第一控制信号，具有高于高输入阈值电平的电平的第二控制信号，以及具有处于低输入阈值电平和高输入阈值电平之间的中间电平的第三控制信号。该计数器具有非常大的容量，结构简单，并且对模拟和数字信号都有效。

2. 发明申请

US20110311017A1 CLOCK GLITCH DETECTION 有权
标题翻译：时钟检测
公开(公告)号：US20110311017A1
公开(公告)日：2011-12-22
申请号：US13148487
申请日：2009-03-31
申请人： Markus Baumeister , Joachim Kruecken , Rolf Schlagenhaft
发明人： Markus Baumeister , Joachim Kruecken , Rolf Schlagenhaft
IPC分类号： H03K25/12
CPC分类号： G06F1/10
摘要： A circuit comprises a clock tree for distributing a clock signal. A first counter is arranged at a first point in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first current count equal to a first delayed count. After a first delay, the first counter sets the first delayed count equal to the first current count plus an increment. A second counter is arranged at a second point in the clock tree. Upon detecting a triggering edge in the clock signal, the second counter sets a second current count equal to a second delayed count. After a second delay, the second counter sets the second delayed count equal to the second current count plus the increment. A comparator compares the first current count and the second current count. The first point and the second point are not the same, or the second delay is longer than the first delay.
摘要翻译：电路包括用于分配时钟信号的时钟树。第一个计数器被布置在时钟树的第一个点。当检测到时钟信号中的触发边沿时，第一计数器设置等于第一延迟计数的第一当前计数。在第一延迟之后，第一计数器将第一延迟计数设置为等于第一当前计数加上增量。第二个计数器被布置在时钟树的第二个点。在检测到时钟信号中的触发边沿时，第二计数器设置等于第二延迟计数的第二当前计数。在第二延迟之后，第二计数器将第二延迟计数设置为等于第二当前计数加上增量。比较器比较第一当前计数和第二当前计数。第一点和第二点不相同，或者第二个延迟比第一个延迟长。

3. 发明授权

US3518447A Electronic timer with magnetic core counter and reset circuit 失效
标题翻译：具有磁芯计数器和复位电路的电子定时器
公开(公告)号：US3518447A
公开(公告)日：1970-06-30
申请号：US3518447D
申请日：1966-03-04
申请人： US ARMY
发明人： GURTLER EDWARD A
IPC分类号： H03K25/00 , H03K25/02 , H03K25/12 , H03K25/18 , H03K29/00
CPC分类号： H03K25/02 , H03K25/00 , H03K25/12

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