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1. 发明授权

US06611474B2 Semiconductor device 有权
公开(公告)号：US06611474B2
公开(公告)日：2003-08-26
申请号：US10201317
申请日：2002-07-24
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C11407
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085
摘要： A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.

2. 发明授权

US06243303B1 Method and circuitry for writing data 有权
标题翻译：用于写入数据的方法和电路
公开(公告)号：US06243303B1
公开(公告)日：2001-06-05
申请号：US09626986
申请日：2000-07-27
申请人： Sanjay K. Sancheti , George M. Ansel , William G. Baker , James E. Kelly
发明人： Sanjay K. Sancheti , George M. Ansel , William G. Baker , James E. Kelly
IPC分类号： G11C11407
CPC分类号： G11C7/1078
摘要： A method of generating write control signals insensitive to glitches on a data input signal comprising the steps of (A) enabling a write of a first or second value in response to a data input transition, (B) holding in a ready state until the data input is stable and (C) writing stable data into a memory array.
摘要翻译：一种产生对数据输入信号上的毛刺不敏感的写入控制信号的方法，包括以下步骤：（A）响应于数据输入转换使第一或第二值写入，（B）保持就绪状态直到数据输入稳定，（C）将稳定数据写入存储器阵列。

3. 发明授权

US06452858B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06452858B1
公开(公告)日：2002-09-17
申请号：US09706374
申请日：2000-11-03
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C11407
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085
摘要： A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.
摘要翻译：一种半导体器件，用于将三电平的电压输出到字驱动器，同时减轻MOS晶体管中的击穿电压。本发明包括插入字驱动器中的击穿电压降低MOS晶体管和两个NMOS晶体管，以将读出电压提供给字线。此外，字驱动器通过主字线和公用字线上的不同电压幅度进行控制。

4. 发明授权

US06198687B1 Semiconductor memory device having a plurality of transfer gates and improved word line and column select timing for high speed write operations 失效
标题翻译：具有多个传输门的半导体存储器件和用于高速写入操作的改进的字线和列选择定时
公开(公告)号：US06198687B1
公开(公告)日：2001-03-06
申请号：US08716884
申请日：1996-09-20
申请人： Koji Sakui , Kazunori Ohuchi , Fujio Masuoka
发明人： Koji Sakui , Kazunori Ohuchi , Fujio Masuoka
IPC分类号： G11C11407
CPC分类号： G11C8/18
摘要： A semiconductor memory device which receives a row address strobe (RAS) signal and a column address strobe (CAS) signal from an external device. The device includes rewritable memory cells formed on a semiconductor substrate, a plurality of bit lines, a plurality of word lines, and a transfer gate coupled between the bit lines and input/output (I/O) lines and controlled by a column select line or signal. In one embodiment, a first transfer gate is connected between the bit lines and a second transfer gate, the second transfer gate connected between the first transfer gate and an input/output (I/O) line and controlled by a column select line (CSL). A third transfer gate may also by provided. The first transfer gate is driven in response to a clock signal which is enabled at substantially the same time as a word line of the plurality of word lines is selected during both read and write cycles. Thus, during a write cycle in which the CAS signal is enabled prior to the RAS signal, a selected CSL can be increased from a first voltage (VSS) to one of a second voltage (Vdd) and {fraction (3/2)} Vdd as soon as a column address is input.
摘要翻译：从外部设备接收行地址选通（RAS）信号和列地址选通（CAS）信号的半导体存储器件。该器件包括形成在半导体衬底上的可重写存储单元，多个位线，多个字线和耦合在位线和输入/输出（I / O）线之间并由列选择线控制的传输栅极或信号。在一个实施例中，第一传输门连接在位线和第二传输门之间，第二传输门连接在第一传输门和输入/输出（I / O）线之间，并由列选择线（CSL ）。也可以通过提供第三传输门。响应于在读取和写入周期期间选择多个字线的字线的基本上相同的时间使能的时钟信号来驱动第一传输门。因此，在RAS信号之前的CAS信号被使能的写周期中，所选择的CSL可以从第一电压（VSS）增加到第二电压（Vdd）和{分数（3/2）}之一一旦列地址被输入，就会Vdd。

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