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1. 发明申请

US20110122977A1 SELF-COMPENSATING DRIFT-FREE HIGH-FREQUENCY PHASE DETECTOR CIRCUIT 有权
标题翻译：自补偿无高速高频相位检测电路
公开(公告)号：US20110122977A1
公开(公告)日：2011-05-26
申请号：US12301950
申请日：2007-05-21
申请人： Frank Ludwig
发明人： Frank Ludwig
IPC分类号： H04L1/00
CPC分类号： H03D13/007
摘要： The present invention relates to a phase detector circuit (10) having an RF distribution device (20) which is intended to receive two sinusoidal high-frequency signals (RF, LO) with an input phase difference (φRF(t)−φLO(t)) and comprises two power splitters (21, 22) in order to split the two high-frequency signals (RF, LO) into two respective parts, a self-calibrating phase detector module (30) which is configured to receive one respective part of the two high-frequency signals which have been split, a low-noise phase detector module (40) which is configured to receive the respective other part of the high-frequency signals which have been split, and a complementary filter device (50) which is configured to receive the output signals from the self-calibrating phase detector module (30) and the low-noise phase detector module (40) and to output a signal which indicates the time-dependent input phase difference between the two high-frequency signals (RF, LO).
摘要翻译：本发明涉及一种具有RF分配装置（20）的相位检测器电路（10），该RF分配装置旨在接收具有输入相位差的两个正弦高频信号（RF，LO）（＆phgr; RF（t） - ＆phgr ; LO（t）），并且包括两个功率分配器（21,22），以便将两个高频信号（RF，LO）分成两个相应部分;自校准相位检测器模块（30），其被配置为接收已经被分离的两个高频信号的相应部分;低噪声相位检测器模块（40），被配置为接收已经被分离的高频信号的相应的另一部分;以及互补滤波器设备（50），其被配置为从所述自校准相位检测器模块（30）和所述低噪声相位检测器模块（40）接收所述输出信号，并且输出指示所述自校准相位检测器模块两个高频信号（RF，LO）。

2. 发明授权

US06064236A Phase detector and timing extracting circuit using phase detector 失效
标题翻译：相位检测器和定时提取电路采用相位检测器
公开(公告)号：US06064236A
公开(公告)日：2000-05-16
申请号：US39595
申请日：1998-03-16
申请人： Naoki Kuwata , Takuji Yamamoto
发明人： Naoki Kuwata , Takuji Yamamoto
IPC分类号： H03K5/00 , H03D13/00 , H03L7/089 , H04L7/027 , H04L7/033
CPC分类号： H03D13/003 , H03D13/007 , H03L7/089 , H04L7/033 , H04L7/027
摘要： Disclosed are a phase detector for detecting the phase difference between a data signal and a clock signal, and a timing extracting circuit for controlling the phase of the clock signal so that the phase relationship between the clock signal and the data signal is optimal by using the phase detector. The phase detector includes an edge detector for generating an edge signal at the rising edge and the falling edge of the data signal, and a D flip flop (D-FF) for storing and outputting the logical value of the clock signal at the time of generation of the edge signal, and holding the logical value until the generation of the next edge signal, thereby outputting a signal corresponding to the phase difference between the data signal and the clock signal. A clock generator in the timing extracting circuit having a PLL structure controls the phase of the clock signal so that the difference becomes optimal.
摘要翻译：公开了一种用于检测数据信号和时钟信号之间的相位差的相位检测器，以及用于控制时钟信号的相位的定时提取电路，使得时钟信号和数据信号之间的相位关系通过使用相位检测器。相位检测器包括用于在数据信号的上升沿和下降沿产生边沿信号的边沿检测器，以及用于存储和输出时钟信号的逻辑值的D触发器（D-FF）生成边缘信号，并保持逻辑值直到生成下一个边沿信号，从而输出与数据信号和时钟信号之间的相位差对应的信号。具有PLL结构的定时提取电路中的时钟发生器控制时钟信号的相位，使得差值变得最佳。

3. 发明授权

US3678185A Semiconductor circuit for phase comparison 失效
标题翻译：用于相位比较的半导体电路
公开(公告)号：US3678185A
公开(公告)日：1972-07-18
申请号：US3678185D
申请日：1971-03-12
申请人： SONY CORP
发明人： OKADA TAKASHI
IPC分类号： H03D3/00 , H03D1/22 , H03D5/00 , H03D13/00 , H04N5/12 , H04N9/66 , H04N9/50
CPC分类号： H04N9/66 , H03D1/229 , H03D13/007 , H04N5/126
摘要： A semiconductor circuit for phase comparison which is devoid of capacitors and hence is suitable for use in an integrated circuit network, comprises a pair of transistors of the same conductivity type connected in the form of a differential amplifier and first and second bridging circuits including groups of series connected diodes and extending between one electrode of one of the transistors and the same electrode of the other transistor. The two input signals which are to be phase compared with each other are respectively supplied to one of the transistors and to the first bridging circuit, and a compared output signal is picked up from the second bridging circuit.
摘要翻译：一种用于相位比较的半导体电路，其不含电容器，因此适用于集成电路网络，包括以差分放大器形式连接的相同导电类型的一对晶体管，以及第一和第二桥接电路，包括：串联连接的二极管并且在一个晶体管的一个电极和另一个晶体管的相同电极之间延伸。要相互比较的两个输入信号分别提供给晶体管中的一个和第一桥接电路，并且从第二桥接电路拾取比较的输出信号。

4. 发明授权

US07333779B2 PLL circuit and radio communication terminal apparatus using the same 有权
标题翻译： PLL电路和使用其的无线通信终端装置
公开(公告)号：US07333779B2
公开(公告)日：2008-02-19
申请号：US11121018
申请日：2005-05-04
申请人： Taizo Yamawaki , Takefumi Endo , Kazuo Watanabe , Kazuaki Hori , Julian Hildersley
发明人： Taizo Yamawaki , Takefumi Endo , Kazuo Watanabe , Kazuaki Hori , Julian Hildersley
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
摘要翻译：在PLL电路中，将LPF的数量减少到一个，以减少安装面积和引脚数量，并简化设计。在一个实施例中，PLL电路包括可变增益相位比较器，混频器，LPF，VCO，耦合器以及控制VCO的开/关操作的控制电路。可变增益相位比较器能够改变相位差增益。 VCO的操作的开/关由控制电路控制，使得VCO中的一个被关断。相位差转换增益根据VCO的灵敏度而变化，因此PLL电路所需的LPF的数量可以减少到一个。

5. 发明申请

US20050215222A1 PLL circuit and radio communication terminal apparatus using the same 有权
公开(公告)号：US20050215222A1
公开(公告)日：2005-09-29
申请号：US11121018
申请日：2005-05-04
申请人： Taizo Yamawaki , Takefumi Endo , Kazuo Watanabe , Kazuaki Hori , Julian Hildersley
发明人： Taizo Yamawaki , Takefumi Endo , Kazuo Watanabe , Kazuaki Hori , Julian Hildersley
IPC分类号： H03L7/10 , H03D13/00 , H03L7/00 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/16 , H03L7/18 , H04B1/3822 , H04B1/40 , H04L7/033
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.

6. 发明授权

US4488109A Phase detectors for detecting a mutual phase difference between two signals 失效
标题翻译：用于检测两个信号之间的相位差的相位检测器
公开(公告)号：US4488109A
公开(公告)日：1984-12-11
申请号：US456503
申请日：1983-01-07
申请人： Takashi Otobe , Yasutoshi Komatsu , Yoshikazu Murakami
发明人： Takashi Otobe , Yasutoshi Komatsu , Yoshikazu Murakami
IPC分类号： H03D9/04 , H03D13/00 , G01R25/00
CPC分类号： H03D13/007 , H03D13/00
摘要： A phase detector for detecting a mutual phase difference between two signals, such as first and second microwave signals, comprises first and second signal paths for being supplied with first and second input signals of the same frequency, respectively, and providing with a predetermined additional mutual phase difference between the first and second input signals at their output ends and a field effect transistor having a pair of input electrodes connected to the output ends of the first and second signal paths, respectively, and an output electrode from which an output signal representing a mutual phase difference which the first and second input signals have originally therebetween is derived. The first and second input signals at the input electrodes of the field effect transistor have the original mutual phase difference which is to be detected and the predetermined additional mutual phase difference added by the first and second signal paths therebetween. The field effect transistor is biased to operate with a gate bias voltage nearly equal to a pinch-off voltage thereof. In order to establish such biasing state without reducing the operational gain of the field effect transistor, a biasing resistance connected to the source of the field effect transistor is selected to be low and a current source is provided for supplying an external biasing current to the biasing resistance, thereby to produce the gate bias voltage required.
摘要翻译：用于检测诸如第一和第二微波信号的两个信号之间的相互相位差的相位检测器包括分别被提供有相同频率的第一和第二输入信号的第一和第二信号路径，并且提供预定的附加相互在其输出端处的第一和第二输入信号之间的相位差和分别连接到第一和第二信号路径的输出端的一对输入电极的场效应晶体管和输出电极，输出信号表示导出第一和第二输入信号之间的相互相位差。场效应晶体管的输入电极处的第一和第二输入信号具有待检测的原始相位差和由它们之间的第一和第二信号路径相加的预定附加相位差。场效应晶体管被偏置以以几乎等于其夹断电压的栅极偏置电压工作。为了在不降低场效应晶体管的操作增益的情况下建立这种偏置状态，连接到场效应晶体管的源极的偏置电阻被选择为低，并且提供电流源以向偏置电压提供外部偏置电流电阻，从而产生所需的栅极偏置电压。

7. 发明授权

US2736803A Frequency control 失效
公开(公告)号：US2736803A
公开(公告)日：1956-02-28
申请号：US14969250
申请日：1950-03-15
申请人： HARTFORD NAT BANK & TRUST CO
发明人： HERMAN HUGENHOLTZ EDUARD
IPC分类号： H01J31/06 , H03C3/09 , H03D13/00 , H03K7/04 , H03L7/08
CPC分类号： H03L7/08 , H01J31/06 , H03C3/09 , H03D13/007 , H03K7/04

8. 发明申请

US20130038351A1 PHASE DETECTOR 有权
标题翻译：相位检测器
公开(公告)号：US20130038351A1
公开(公告)日：2013-02-14
申请号：US13206138
申请日：2011-08-09
申请人： Marc Gerardus Maria Stegers , Arie van Staveren
发明人： Marc Gerardus Maria Stegers , Arie van Staveren
IPC分类号： H03D13/00
CPC分类号： H03D13/007
摘要： A phase detection system for providing a phase signal indicative of a phase difference between first and second input signals, with the system including a pair of amplification channels for receiving the input signals, with each channel including a plurality of amplifier stages. The outputs of the two amplification channels are connected to the inputs of a multiplier arrangement, with the arrangement producing an uncompensated phase signal. Compensation circuitry is provided to receive a magnitude signal indicative of the relative magnitudes of the two input signals, with the magnitude signal being used to produce a corrected phase signal indicative of the phase difference between the two input signals.
摘要翻译：一种相位检测系统，用于提供指示第一和第二输入信号之间的相位差的相位信号，该系统包括用于接收输入信号的一对放大通道，每个通道包括多个放大器级。两个放大通道的输出端连接到乘法器装置的输入端，该布置产生无补偿的相位信号。提供补偿电路以接收指示两个输入信号的相对幅度的幅度信号，其中幅度信号用于产生指示两个输入信号之间的相位差的校正的相位信号。

9. 发明申请

US20010010461A1 Phase comparator 失效
标题翻译：相位比较器
公开(公告)号：US20010010461A1
公开(公告)日：2001-08-02
申请号：US09734286
申请日：2000-12-11
发明人： Meng-Huang Chu
IPC分类号： G01D001/14
CPC分类号： H03D13/007
摘要： A phase comparator for calculating the phase difference between a test wave form and an output wave form in a disk driver according to the invention includes a phase converter, a first multiplier, a first integrator, a second multiplier, a second integrator and a phase angle calculator. The phase converter for delaying the test wave form for a specific time based on the frequency thereof. The first multiplier electrically coupled to the phase converter for performing a first operation by multiplying the delayed test wave form with the output wave form. The first integrator electrically coupled to the first multiplier for integrating the result of the first operation for a period to generate a first weighted value. The second multiplier for performing a second operation by multiplying the test wave form with the output wave form. The second integrator electrically coupled to the second multiplier for integrating the result of the second operation for the same period to generate a second weighted value. The phase angle calculator electrically coupled to the first integrator and the second integrator for receiving the first weighted value and the second weighted value and then outputting a value representing the phase difference between the test wave function and the output wave form.
摘要翻译：根据本发明的用于计算测试波形和输出波形之间的相位差的相位比较器包括相位转换器，第一乘法器，第一积分器，第二乘法器，第二积分器和相位角计算器用于根据其频率将测试波形延迟特定时间的相位转换器。第一乘法器电耦合到相位转换器，用于通过将延迟的测试波形与输出波形相乘来执行第一操作。第一积分器电耦合到第一乘法器，用于将第一操作的结果积分一段时间以产生第一加权值。用于通过将测试波形与输出波形相乘来执行第二操作的第二乘法器。第二积分器电耦合到第二乘法器，用于对相同周期的第二操作的结果进行积分，以产生第二加权值。所述相位角计算器电耦合到第一积分器和第二积分器，用于接收第一加权值和第二加权值，然后输出表示测试波函数和输出波形之间的相位差的值。

10. 发明授权

US3771063A Bi-polar phase detector 失效
标题翻译：双极相位检测器
公开(公告)号：US3771063A
公开(公告)日：1973-11-06
申请号：US3771063D
申请日：1972-03-13
申请人： CALNOR EL PASO INC
发明人： BARRETT R
IPC分类号： H03D13/00 , H03B3/04
CPC分类号： H03D13/007
摘要： A phase detector employs a pair of operational amplifiers for establishing equal amplitudes for a reference signal and the signal of which the phase is to be measured. The reference signal alternately blocks an unblocks a diode bridge to provide a linear bi-polar output signal proportional to the difference in phase between the two input signals.
摘要翻译：相位检测器采用一对运算放大器，用于为参考信号和相位测量的信号建立相等的幅度。参考信号交替地阻止二极管桥接器阻塞以提供与两个输入信号之间的相位差成比例的线性双极输出信号。

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