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1. 发明申请

US20160043218A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：US20160043218A1
公开(公告)日：2016-02-11
申请号：US14452191
申请日：2014-08-05
申请人： Semiconductor Components Industries, LLC
发明人： Peter Moens , Chun-Li Liu
IPC分类号： H01L29/78 , H01L29/06 , H01L21/02 , H01L29/66 , H01L21/285 , H01L29/417 , H01L21/768 , H01L29/20 , H01L21/762
CPC分类号： H01L21/76898 , H01L21/0217 , H01L21/02178 , H01L21/743 , H01L21/746 , H01L21/7605 , H01L21/76224 , H01L21/763 , H01L29/2003 , H01L29/407 , H01L29/4175 , H01L29/66318 , H01L29/7786
摘要： In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.
摘要翻译：根据实施例，半导体部件的制造方法包括通过多层化合物半导体材料形成第一沟槽。绝缘材料形成在第一沟槽的第一和第二侧壁以及第二沟槽的第一和第二侧壁上，沟槽填充材料形成在第一和第二沟槽中。根据另一实施例，半导体部件包括半导体材料体上的多层化合物半导体材料以及延伸到多层化合物半导体材料中的第一和第二填充沟槽。第一沟槽具有第一和第二侧壁以及在第一和第二侧壁上方的底板和第一电介质衬垫，并且第二沟槽具有第一和第二侧壁以及位于第二沟槽的第一和第二侧壁上的底板和第二电介质衬垫。

2. 发明授权

US5292686A Method of forming substrate vias in a GaAs wafer 失效
标题翻译：在GaAs晶片中形成衬底通孔的方法
公开(公告)号：US5292686A
公开(公告)日：1994-03-08
申请号：US810740
申请日：1991-12-18
申请人： Susan Riley , Terri L. Clayton
发明人： Susan Riley , Terri L. Clayton
IPC分类号： H01L21/74 , H01L21/26
CPC分类号： H01L21/76898 , H01L21/746 , Y10S438/94 , Y10S438/975 , Y10S438/977
摘要： A method of forming substrate vias in a GaAs wafer begins with a GaAs wafer in which all top side processing steps are complete. The top surface of the GaAs wafer includes top surface via contacts, which are in electrical contact with the bottom surface ground plane once the ground vias are complete. A protective layer is formed on the top surface of the wafer to protect the finished integrated circuitry. A portion of the substrate is removed from the bottom surface to achieve a thin layer of substrate material. The bottom surface of the thinned substrate is metalized with a first metal layer. Laser via holes are drilled into the thinned substrate from the bottom surface of the wafer to within a few microns from the top surface metal via contacts. The laser holes are drilled by emitting a controlled number of single pulses over the selected via location. The substrate vias are subsequently wet etched to remove the remaining substrate thickness and the bottom surface of the wafer and the substrate via holes are metalized with a second metal layer. The second metal layer fills the via holes and establishes electrical contact between the top surface via contacts and the bottom surface ground plane. In a final step, the protective layer is removed from the top surface of the wafer.
摘要翻译：在GaAs晶片中形成衬底通孔的方法从其中所有顶侧处理步骤完成的GaAs晶片开始。 GaAs晶片的顶表面包括顶表面通孔触点，一旦接地孔完成，它们与底表面接地平面电接触。在晶片的顶表面上形成保护层以保护成品集成电路。衬底的一部分从底表面去除以获得薄的衬底材料层。薄化基板的底表面用第一金属层金属化。将激光通孔从晶片的底表面钻到减薄的基板中，通过触点从顶表面金属到几微米。通过在所选择的通孔位置上发射受控数量的单个脉冲来钻出激光孔。随后湿法蚀刻衬底通孔以去除剩余的衬底厚度，并且晶片的底表面和衬底通孔用第二金属层金属化。第二金属层填充通孔，并通过触点和底表面接地层在顶表面之间建立电接触。在最后的步骤中，从晶片的顶表面去除保护层。

3. 发明授权

US12119309B2 Enhanced bonding between III-V material and oxide material 有权
公开(公告)号：US12119309B2
公开(公告)日：2024-10-15
申请号：US17683725
申请日：2022-03-01
申请人： OpenLight Photonics, Inc.
发明人： Avi Feshali , John Hutchinson
IPC分类号： H01L23/00 , H01L21/02 , H01L21/306 , H01L21/74 , H01L27/12 , H01L29/06 , H01L29/20
CPC分类号： H01L23/564 , H01L21/02164 , H01L21/306 , H01L21/746 , H01L27/1203 , H01L29/0649 , H01L29/20
摘要： When III-V semiconductor material is bonded to an oxide material, water molecules can degrade the bonding if they become trapped at the interface between the III-V material and the oxide material. Because water molecules can diffuse readily through oxide material, and may not diffuse as readily through III-V material or through silicon, forcing the III-V material against the oxide material can force water molecules at the interface into the oxide material and away from the interface. Water molecules present at the interface can be forced during manufacturing through vertical channels in a silicon layer into a buried oxide layer thereby to enhance bonding between the III-V material and the oxide material. Water molecules can be also forced through lateral channels in the oxide material, past a periphery of the III-V material, and, through diffusion, out of the oxide material into the atmosphere.

4. 发明授权

US10840334B2 Gallium nitride high-electron mobility transistors with deep implanted p-type layers in silicon carbide substrates for power switching and radio frequency applications and process for making the same 有权
公开(公告)号：US10840334B2
公开(公告)日：2020-11-17
申请号：US16260095
申请日：2019-01-28
申请人： Cree, Inc.
发明人： Saptharishi Sriram , Thomas Smith , Alexander Suvorov , Christer Hallin
IPC分类号： H01L29/10 , H01L29/16 , H01L29/20 , H01L29/205 , H01L29/40 , H01L29/788 , H01L21/74 , H01L29/66 , H01L29/778 , H01L29/417
CPC分类号： H01L29/1087 , H01L21/743 , H01L21/746 , H01L29/1075 , H01L29/1083 , H01L29/1608 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/66462 , H01L29/7783 , H01L29/7787 , H01L29/1066 , H01L29/41766
摘要： The disclosure is directed to a high-electron mobility transistor that includes a SiC substrate layer, a GaN buffer layer arranged on the SiC substrate layer, and a p-type material layer having a length parallel to a surface of the SiC substrate layer over which the GaN buffer layer is provided. The p-type material layer is provided in one of the following: the SiC substrate layer and a first layer arranged on the SiC substrate layer. A method of making the high-electron mobility transistor is also disclosed.

5. 发明授权

US08390091B2 Semiconductor structure, an integrated circuit including a semiconductor structure and a method for manufacturing a semiconductor structure 有权
标题翻译：半导体结构，包括半导体结构的集成电路和半导体结构的制造方法
公开(公告)号：US08390091B2
公开(公告)日：2013-03-05
申请号：US13143548
申请日：2009-02-03
申请人： Philippe Renaud
发明人： Philippe Renaud
IPC分类号： H01L29/47
CPC分类号： H01L29/0847 , H01L21/746 , H01L27/0605 , H01L27/0629 , H01L29/2003 , H01L29/4175 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7787 , H01L29/872
摘要： A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal. The structure further includes a vertical Schottky diode, including: an anode; a cathode including the substrate, and a Schottky barrier between the cathode and the anode, the Schottky barrier being situated between the substrate and a anode layer in the stack of layers.
摘要翻译：单片半导体结构包括一叠层。堆叠包括基板; 由第一半导体材料制成的第一层; 以及由第二半导体材料制成的第二层。第一层位于衬底和第二层之间，并且第一半导体材料和第二半导体材料中的至少一个含有III族氮化物材料。该结构包括功率晶体管，其包括形成在层叠层中的主体; 位于所述第一层的面向所述第二层的一侧的第一电源端子; 至少部分地形成在所述基板中的第二电源端子; 以及栅极结构，用于控制在第一电力端子和第二电力端子之间通过主体的电信号的传播。该结构还包括垂直肖特基二极管，包括：阳极; 包括衬底的阴极和在阴极和阳极之间的肖特基势垒，肖特基势垒位于衬底和堆叠层中的阳极层之间。

6. 发明申请

US20110278598A1 SEMICONDUCTOR STRUCTURE, AN INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE 有权
标题翻译：半导体结构，包括半导体结构的集成电路和制造半导体结构的方法
公开(公告)号：US20110278598A1
公开(公告)日：2011-11-17
申请号：US13143548
申请日：2009-02-03
申请人： Philippe Renaud
发明人： Philippe Renaud
IPC分类号： H01L29/16 , H01L29/20 , H01L21/329 , H01L29/778
CPC分类号： H01L29/0847 , H01L21/746 , H01L27/0605 , H01L27/0629 , H01L29/2003 , H01L29/4175 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7787 , H01L29/872
摘要： A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal. The structure further includes a vertical Schottky diode, including: an anode; a cathode including the substrate, and a Schottky barrier between the cathode and the anode, the Schottky barrier being situated between the substrate and a anode layer in the stack of layers.
摘要翻译：单片半导体结构包括一叠层。堆叠包括基板; 由第一半导体材料制成的第一层; 以及由第二半导体材料制成的第二层。第一层位于衬底和第二层之间，并且第一半导体材料和第二半导体材料中的至少一个含有III族氮化物材料。该结构包括功率晶体管，其包括形成在层叠层中的主体; 位于所述第一层的面向所述第二层的一侧的第一电源端子; 至少部分地形成在所述基板中的第二电源端子; 以及栅极结构，用于控制在第一电力端子和第二电力端子之间通过主体的电信号的传播。该结构还包括垂直肖特基二极管，包括：阳极; 包括衬底的阴极和在阴极和阳极之间的肖特基势垒，肖特基势垒位于衬底和堆叠层中的阳极层之间。

7. 发明公开

US20240204055A1 SCREEN LAYER INTEGRATION IN GALLIUM NITRIDE TECHNOLOGY 审中-公开
公开(公告)号：US20240204055A1
公开(公告)日：2024-06-20
申请号：US18067705
申请日：2022-12-17
申请人： Texas Instruments Incorporated
发明人： Dong Seup Lee
IPC分类号： H01L29/10 , H01L21/265 , H01L21/266 , H01L21/74 , H01L29/20 , H01L29/205 , H01L29/66 , H01L29/778
CPC分类号： H01L29/1075 , H01L21/26546 , H01L21/266 , H01L21/743 , H01L21/746 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786
摘要： A microelectronic device includes a lower buffer layer of III-N semiconductor material formed over a silicon substrate. A screen layer having free charge carriers is formed over the lower buffer layer. The microelectronic device may include an upper buffer layer of III-N semiconductor material formed over the screen layer. A gallium nitride field effect transistor (GaN FET) is formed over the screen layer. The GaN FET has a two-dimensional electron gas (2DEG) layer directly over at least a portion of the screen layer. The screen layer may include a doped layer of III-N semiconductor material, or a buried barrier layer with 2DEG layers in the lower and upper buffer layers. The screen layer is electrically connected to a current node, that is, a source node or a drain node, of the GaN FET.

8. 发明授权

US09627530B2 Semiconductor component and method of manufacture 有权
公开(公告)号：US09627530B2
公开(公告)日：2017-04-18
申请号：US14452222
申请日：2014-08-05
申请人： Semiconductor Components Industries, LLC
发明人： Chun-Li Liu , Balaji Padmanabhan , Ali Salih , Peter Moens
IPC分类号： H01L21/02 , H01L29/78 , H01L21/762 , H01L29/417 , H01L21/768 , H01L29/66 , H01L21/74 , H01L21/76 , H01L29/778 , H01L29/20 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7827 , H01L21/743 , H01L21/746 , H01L21/7605 , H01L21/76224 , H01L21/763 , H01L21/76898 , H01L29/0607 , H01L29/0649 , H01L29/1075 , H01L29/2003 , H01L29/4175 , H01L29/66318 , H01L29/66462 , H01L29/66666 , H01L29/7786
摘要： In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

9. 发明申请

US20160043219A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
公开(公告)号：US20160043219A1
公开(公告)日：2016-02-11
申请号：US14452222
申请日：2014-08-05
申请人： Semiconductor Components Industries, LLC
发明人： Chun-Li Liu , Balaji Padmanabhan , Ali Salih , Peter Moens
IPC分类号： H01L29/78 , H01L21/02 , H01L29/417 , H01L29/40 , H01L29/66 , H01L29/20 , H01L29/06 , H01L21/762 , H01L21/285 , H01L21/768
CPC分类号： H01L29/7827 , H01L21/743 , H01L21/746 , H01L21/7605 , H01L21/76224 , H01L21/763 , H01L21/76898 , H01L29/0607 , H01L29/0649 , H01L29/1075 , H01L29/2003 , H01L29/4175 , H01L29/66318 , H01L29/66462 , H01L29/66666 , H01L29/7786
摘要： In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

10. 发明申请

US20160043185A1 SEMICONDUCTOR COMPONENT AND METHOD 有权
标题翻译：半导体元件和方法
公开(公告)号：US20160043185A1
公开(公告)日：2016-02-11
申请号：US14452162
申请日：2014-08-05
申请人： Semiconductor Components Industries, LLC
发明人： Chun-Li Liu
IPC分类号： H01L29/40 , H01L21/74 , H01L21/02
CPC分类号： H01L21/743 , H01L21/02304 , H01L21/746 , H01L29/2003 , H01L29/205 , H01L29/401 , H01L29/404 , H01L29/872
摘要： In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface and forming a passivation layer on the semiconductor material Portions of the passivation layer are removed and portions of the semiconductor material exposed by removing the portions of the passivation layer are also removed. A layer of dielectric material is formed on the passivation layer and the exposed portions of the semiconductor material and first and second cavities are formed in the layer of dielectric material. The first cavity exposes a first portion of the semiconductor material and has at least one step shaped sidewall and the second cavity exposes a second portion of the semiconductor material. A first electrode is formed in the first cavity and a second electrode is formed in the second cavity.
摘要翻译：根据实施例，制造半导体部件的方法包括提供具有表面并在半导体材料上形成钝化层的半导体材料，去除钝化层的部分，并且通过去除部分钝化层也被去除。在钝化层上形成介电材料层，半导体材料的暴露部分和第一和第二空腔形成在电介质材料层中。第一腔暴露半导体材料的第一部分并且具有至少一个阶梯形侧壁，并且第二腔暴露半导体材料的第二部分。第一电极形成在第一腔中，第二电极形成在第二腔中。

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