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1. 发明授权

US10502862B2 Combined chemical and velocity sensors for fluid contamination analysis 有权
公开(公告)号：US10502862B2
公开(公告)日：2019-12-10
申请号：US15597648
申请日：2017-05-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bruce G. Elmegreen
IPC分类号： G01V9/00 , G06F7/64 , G01P5/00
CPC分类号： G01V9/00 , G01P5/001 , G01V9/007 , G06F7/64
摘要： Methods and systems for locating a chemical source include measuring chemical concentration with sensors at a plurality of different positions. Measurements from pairs of positions are cross-correlated to determine an average velocity vector for a group of positions. A convergence region is determined based on a plurality of average velocity vectors to determine a chemical source location.

2. 发明授权

US09298421B2 Performing quotient selection for a carry-save division operation 有权
标题翻译：执行进位保存除法运算的商选择
公开(公告)号：US09298421B2
公开(公告)日：2016-03-29
申请号：US14028943
申请日：2013-09-17
申请人： Oracle International Corporation
发明人： Josephus C. Ebergen , Navaneeth P. Jamadagni , Ivan E. Sutherland
IPC分类号： G06F7/48 , G06F7/64 , G06F7/537
CPC分类号： G06F7/48 , G06F7/5375 , G06F7/64
摘要： The disclosed embodiments disclose techniques for performing quotient selection in an iterative carry-save division operation that divides a dividend, R, by a divisor, D, to produce an approximation of a quotient, Q=R/D. During a divide operation, a divider approximates Q by iteratively selecting an operation to perform for each iteration of the carry-save division operation and then performing the selected operation. The operation for each iteration is selected based on the current partial sum bits of a partial remainder in carry-save form (rs) and the current partial carry bits of a partial remainder in carry-save form (rc). More specifically, the operation is selected from a set of operations that includes: (1) a 2X* operation; (2) an S1 & 2X* operation; (3) an S2 & 2X* operation; (4) an A1 & 2X* operation; and (5) an A2 & 2X* operation.
摘要翻译：所公开的实施例公开了在迭代进位保存除法运算中执行商选择的技术，其将除数R除以除数D以产生商的近似值Q = R / D。在分频操作期间，分频器通过迭代地选择对进位保存除法运算的每次迭代执行的操作，然后执行所选择的操作来逼近Q。基于进位保存格式（rs）的部分余数的当前部分和位和进位保存形式（rc）的部分余数的当前部分进位位，选择每次迭代的操作。更具体地说，从一组操作中选择操作，该操作包括：（1）2X *操作; （2）S1＆2X *操作; （3）S2＆2X *操作; （4）A1＆2X *操作; 和（5）A2＆2X *操作。

3. 发明授权

US08912838B1 Passive offset and overshoot cancellation for sampled data circuits 有权
标题翻译：采样数据电路的被动偏移和过冲消除
公开(公告)号：US08912838B1
公开(公告)日：2014-12-16
申请号：US14156301
申请日：2014-01-15
申请人： Maxim Integrated Products, Inc.
发明人： Hae-Seung Lee
IPC分类号： G06F7/64 , G11C27/02
CPC分类号： G11C27/026 , G06F7/64 , G11C7/06 , H03M1/0607 , H03M1/403 , H03M1/442 , H03M3/356 , H03M3/458
摘要： A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.
摘要翻译：具有有效偏移消除的过零检测器包括一组串联电容器和具有输入端子的放大器。偏置电容器可操作地连接在放大器和串联电容器组之间。开关可操作地连接到输入端子，并且偏移采样电容器可操作地连接到开关。在电荷转移阶段，开关将偏移采样电容连接到放大器的输入端。

4. 发明申请

US20140328466A1 DETECTION APPARATUS FOR DETECTING PHOTONS TAKING PILE-UP EVENTS INTO ACCOUNT 有权
标题翻译：用于检测拍摄活动的照相机的检测装置
公开(公告)号：US20140328466A1
公开(公告)日：2014-11-06
申请号：US14362458
申请日：2012-12-13
申请人： KONINKLIJKE PHILIPS N.V.
发明人： Roland Proksa , Ewald Roessl
IPC分类号： G01T1/17 , G01N23/04
CPC分类号： A61B6/585 , A61B6/4241 , A61B6/5205 , A61B6/5258 , A61B6/582 , A61B2560/0223 , A61B2560/0238 , G01R29/0273 , G01R29/033 , G01R29/0878 , G01R29/24 , G01T1/171 , G01T1/18 , G06F7/64 , H01L27/14856 , H03K5/1252 , H03K5/2463 , H03K21/40
摘要： The invention relates to a detection apparatus (12) for detecting photons. The detection apparatus comprises a pile-up determining unit (15) for determining whether detection signal pulses being indicative of detected photons are caused by a pile-up event or by a non-pile-up event, wherein a detection values generating unit (16) generates detection values depending on the detection signal pulses and depending on the determination whether the respective detection signal pulse is caused by a pile-up event or by a non-pile-up event. In particular, the detection values generating unit can be adapted to reject the detection signal pulses caused by pile-up events while generating the detection values. This allows for an improved quality of the generated detection values.
摘要翻译：本发明涉及一种用于检测光子的检测装置（12）。检测装置包括：堆积确定单元，用于确定是否由堆积事件或非堆积事件引起检测到的光子的指示的检测信号脉冲，其中检测值生成单元（16））根据检测信号脉冲产生检测值，并且取决于各个检测信号脉冲是由堆积事件还是由非堆积事件引起的。特别地，检测值生成单元可以适于在产生检测值的同时拒绝由堆积事件引起的检测信号脉冲。这样可以提高产生的检测值的质量。

5. 发明授权

US4246642A Leaky digital integrator 失效
标题翻译：漏电数字集成商
公开(公告)号：US4246642A
公开(公告)日：1981-01-20
申请号：US5298
申请日：1979-01-22
申请人： D. Thomas Magill
发明人： D. Thomas Magill
IPC分类号： G06F7/64 , H03H15/00 , H03H21/00 , H04B3/06 , H04L25/03 , G06F7/49 , G06F15/31
CPC分类号： G06F7/64 , H03H15/00 , H03H21/00 , H04L25/03038
摘要： A leaky digital integrator comprising an accumulator circuit including an adder having first and second adder input terminals and an adder output terminal, and a shift register coupling the adder output terminal back to the second adder input terminal and to an integrator output terminal; a ternary signal detection circuit coupled to the integrator output terminal and operative to develop one of three decay factor signals depending upon whether the integrator output signal level is above, equal to or below a predetermined reference level; and switching apparatus having a first switched terminal which is periodically coupled at a first rate to the first adder input terminal to input update data signals to the accumulator circuit and a second switched terminal which is periodically coupled at a second rate to the first adder input terminal to input decay data signals to the accumulator circuit such that the circuit as a whole performs according to the equationa.sub.i (t)=Da.sub.i (t-1)+.DELTA.a.sub.i (t)where a.sub.i (t) is the integrator output at time t, D is the decay factor and .DELTA.a.sub.i (t) is the update increment.
摘要翻译：一种泄漏数字积分器，包括一个累加器电路，该累加器电路包括一个具有第一加法器输入端和第二加法器输入端的加法器和一个加法器输出端，以及将加法器输出端耦合回第二加法器输入端的移位寄存器和积分器输出端; 耦合到积分器输出端子的三元信号检测电路，用于根据积分器输出信号电平是否高于等于或低于预定参考电平来开发三个衰减因子信号之一; 以及具有第一开关端子的开关装置，其以第一速率周期性地耦合到第一加法器输入端子，以将更新数据信号输入到累加器电路;以及第二开关端子，其以第二速率周期性耦合到第一加法器输入端子将衰减数据信号输入到累加器电路，使得整个电路根据等式ai（t）= Dai（t-1）+ DELTA ai（t）执行，其中ai（t）是时间t的积分器输出，D是衰减因子，DELTA ai（t）是更新增量。

6. 发明授权

US3676655A Digital function generator for two independent variables with interpolation 失效
标题翻译：具有插值的两个独立变量的数字函数发生器
公开(公告)号：US3676655A
公开(公告)日：1972-07-11
申请号：US3676655D
申请日：1970-07-31
申请人： CHANDLER EVANS INC
发明人： ANCONA ANTHONY
IPC分类号： G06F1/035 , G06F7/62 , G06F7/64 , G06F17/17 , G06F15/34
CPC分类号： G06F1/035 , G06F7/62 , G06F7/64 , G06F17/175
摘要： A digital logic circuit for providing an output signal which is a function of a pair of independent variables is disclosed. The disclosed embodiment includes a two-dimensional function generator which operates as a pulse packet analyzer; the twodimensional function generator providing a binary output signal which is an arbitrary function of a third variable with respect to the actual value of a first variable and a known value of a second variable. The disclosed embodiment also includes circuitry for interpolating the regions between curves as represented by the output of the two-dimensional function generator, as a function of the difference between the actual and known values of the second independent variable, in order to provide a binary signal which may be added to the two-dimensional function generator output to produce the desired output signal.
摘要翻译：公开了一种用于提供作为一对独立变量的函数的输出信号的数字逻辑电路。所公开的实施例包括作为脉冲分组分析器工作的二维函数发生器; 所述二维函数发生器提供二进制输出信号，所述二进制输出信号是相对于第一变量的实际值和第二变量的已知值的第三变量的任意函数。所公开的实施例还包括用于内插由二维函数发生器的输出表示的曲线之间的区域的电路，作为第二独立变量的实际值和已知值之间的差的函数，以便提供二进制信号其可以被添加到二维函数发生器输出以产生期望的输出信号。

7. 发明授权

US3274376A Digital differential analyzer in conjunction with a general purpose computer 失效
标题翻译：数字差分分析仪与通用计算机相结合
公开(公告)号：US3274376A
公开(公告)日：1966-09-20
申请号：US50927155
申请日：1955-05-18
申请人： BENDIX CORP
发明人： EVANS DAVID C , HORRELL MAURICE W
IPC分类号： G06F7/64 , G06F15/78 , H01G4/12
CPC分类号： H01G4/1209 , G06F7/64 , G06F15/78

8. 发明授权

US3109090A Variable increment computer 失效
标题翻译：可变增量计算机
公开(公告)号：US3109090A
公开(公告)日：1963-10-29
申请号：US80964359
申请日：1959-04-29
申请人： GEN ELECTRIC
发明人： CABANISS EDWARD H , PRINCE JOHN S
IPC分类号： G06F7/64 , G06F17/10
CPC分类号： G06F17/10 , G06F7/64

9. 发明授权

US3050251A Incremental computing apparatus 失效
标题翻译：增量计算装置
公开(公告)号：US3050251A
公开(公告)日：1962-08-21
申请号：US68426357
申请日：1957-09-16
申请人： DIGITAL CONTROL SYSTEMS INC
发明人： STEELE FLOYD G
IPC分类号： G06F7/64
CPC分类号： G06F7/64

10. 发明授权

US2994477A Digital integrators 失效
标题翻译：数字集成商
公开(公告)号：US2994477A
公开(公告)日：1961-08-01
申请号：US60633756
申请日：1956-08-27
申请人： BENDIX CORP
发明人： MAX PALEVSKY
IPC分类号： G06F7/64 , G06F7/66
CPC分类号： G06F7/66 , G06F7/64

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