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1. 发明授权

US10951403B2 Updating cryptographic keys stored in non-volatile memory 有权
公开(公告)号：US10951403B2
公开(公告)日：2021-03-16
申请号：US16207207
申请日：2018-12-03
申请人： Winbond Electronics Corporation
发明人： Uri Kaluzhny , Mark Luko
IPC分类号： H04L9/08
摘要： A method is provided for generating a new instance of an N-bit cryptographic key for storage in a non-volatile memory (NVM) in which unprogrammed cells have a particular binary value. The method includes generating a random N-bit updating sequence, and generating the new instance of the N-bit cryptographic key by negating each bit in a current instance of the N-bit cryptographic key that has the particular binary value and differs from a correspondingly-positioned bit in the random N-bit updating sequence, without negating any bits in the current instance of the N-bit cryptographic key that do not have the particular binary value. Other embodiments are also described.

2. 发明授权

US10482036B2 Securely binding between memory chip and host 有权
公开(公告)号：US10482036B2
公开(公告)日：2019-11-19
申请号：US15691758
申请日：2017-08-31
申请人： Winbond Electronics Corporation
发明人： Itay Admon , Nir Tasher
IPC分类号： G06F21/00 , G06F12/14 , G06F16/903 , G06F21/60
摘要： A memory system includes an interface, a non-volatile memory and a controller. The interface is configured to communicate over an unsecured communication link with an external host. The non-volatile memory is pre-programmed with a device identifier and a corresponding initialization key that are additionally stored in a database that resides externally to the memory system, and is securely accessible by the host. The controller is configured to send the device identifier to the host, to receive from the host, via the interface, binding information that was generated in the host, to generate, using at least the received binding information and the pre-programmed initialization key, a first binding key that matches a second binding key that is generated in the host based on an initialization key securely obtained by the host from the database, and to securely communicate with the host over the communication link using the first binding key.

3. 发明授权

US10445001B2 Memory control scheme for flash memory devices 有权
公开(公告)号：US10445001B2
公开(公告)日：2019-10-15
申请号：US15437471
申请日：2017-02-21
申请人： WINBOND ELECTRONICS CORPORATION
发明人： Uri Kaluzhny , Hezi Pereg
IPC分类号： G06F3/06
摘要： A method of controlling access to a flash memory device having multiple sectors divided into multiple blocks of memory, including accepting a virtual block address, calculating a set of possible sectors that can be used for storing data having the virtual block address based on a predefined function, reading meta-data of each sector from the set of possible sectors, wherein the meta-data of a sector includes information for each block in the sector indicating if the block is currently in use and the virtual block address of the data stored in the block, determining the physical block address of the virtual block address if the data is currently stored in a block in the possible sectors or if a block is currently allocated to store the data, wherein the set of possible sectors is distinct for each virtual block address.

4. 发明申请

US20180358061A1 DELAY LOCKED LOOP CIRCUIT AND METHOD OF CONTROLLING SAME 审中-公开
公开(公告)号：US20180358061A1
公开(公告)日：2018-12-13
申请号：US15616435
申请日：2017-06-07
申请人： WINBOND ELECTRONICS CORPORATION
发明人： Myung Chan CHOI
IPC分类号： G11C7/22 , G11C7/12 , H03L7/081
CPC分类号： G11C7/222 , G11C7/12 , H03L7/0812
摘要： A memory device includes a delay locked loop (DLL) circuit to receive an external clock, and delay the external clock by a DLL delay time to provide a DLL clock, an output driver to output the DLL clock as a data strobe signal, and a DLL offset control circuit configured to receive at least one of a plurality of functional statement commands, and adjust the DLL delay tine based on the at least one of the functional statement commands. Each one of the DLL circuit and the output driver is selectively powered according to the at least one of the functional statement commands.

5. 发明申请

US20180196598A1 MEMORY CONTROL SCHEME FOR FLASH MEMORY DEVICES 审中-公开
公开(公告)号：US20180196598A1
公开(公告)日：2018-07-12
申请号：US15437471
申请日：2017-02-21
申请人： WINBOND ELECTRONICS CORPORATION
发明人： Uri KALUZHNY , Hezi PEREG
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0658 , G06F3/0679
摘要： A method of controlling access to a flash memory device having multiple sectors divided into multiple blocks of memory, including accepting a virtual block address, calculating a set of possible sectors that can be used for storing data having the virtual block address based on a predefined function, reading meta-data of each sector from the set of possible sectors, wherein the meta-data of a sector includes information for each block in the sector indicating if the block is currently in use and the virtual block address of the data stored in the block, determining the physical block address of the virtual block address if the data is currently stored in a block in the possible sectors or if a block is currently allocated to store the data, wherein the set of possible sectors is distinct for each virtual block address.

6. 发明申请

US20180011632A1 DATA MANAGEMENT IN MULTIPLY-WRITEABLE FLASH MEMORIES 有权
公开(公告)号：US20180011632A1
公开(公告)日：2018-01-11
申请号：US15206277
申请日：2016-07-10
申请人： WINBOND ELECTRONICS CORPORATION
发明人： Uri Kaluzhny
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F12/0246 , G06F2212/1044 , G06F2212/7202 , G06F2212/7204
摘要： According to the present disclosure is provided a device and method for mapping management in a flash memory based on partitioning the memory to a main address space and a substitute space, each partition comprising locations in the memory that are denoted by at least three statues according to which locations are mapped from the main space to the substitute space while responsively modifying the statuses.

7. 发明授权

US09721675B1 Memory device having input circuit and operating method of same 有权
公开(公告)号：US09721675B1
公开(公告)日：2017-08-01
申请号：US15346807
申请日：2016-11-09
申请人： WINBOND ELECTRONICS CORPORATION
发明人： Myung Chan Choi
IPC分类号： G11C7/10 , G11C29/02 , G11C7/22
CPC分类号： G11C29/023 , G11C7/1006 , G11C7/1051 , G11C7/1084 , G11C7/1093 , G11C7/222 , G11C7/225 , G11C29/02 , G11C29/028 , G11C29/12015 , G11C29/56012 , G11C2207/2254
摘要： An input circuit of a memory device includes an input receiver to receive an input signal, a clock receiver to receive a clock signal, a data latch, an input signal delay path coupled to the input receiver and configured to provide a delayed internal input signal to the data latch, a first clock signal delay path coupled to the clock receiver and configured to provide a first delayed internal clock signal, a second clock signal delay path coupled to the input receiver and configured to provide a second delayed internal clock signal, and a multiplexer coupled to receive and select one of the first delayed internal clock signal and the second delayed internal clock signal in response to a test mode control signal, and to provide the selected signal to the data latch.

8. 发明授权

US09442798B2 NAND flash memory having an enhanced buffer read capability and method of operation thereof 有权
标题翻译： NAND闪存具有增强的缓冲器读取能力及其操作方法
公开(公告)号：US09442798B2
公开(公告)日：2016-09-13
申请号：US14448945
申请日：2014-07-31
申请人： Winbond Electronics Corporation
发明人： Oron Michael , Anil Gupta
IPC分类号： G11C29/00 , G06F11/10 , G11C16/10 , G11C16/26 , G11C29/04
CPC分类号： G06F11/1072 , G06F11/1048 , G06F11/1064 , G11C16/10 , G11C16/26 , G11C2029/0411
摘要： A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.
摘要翻译：适用于连续页面读取的页面缓冲器可以用分区数据寄存器，分区缓存寄存器和合适的ECC电路来实现。分区数据寄存器，分区高速缓存寄存器和相关联的ECC电路也可以用于通过使用修改的页数据读指令和/或缓冲器读指令来实现页读操作的实质性改进，包括在一些实现中使用一个分区忙位。

9. 发明申请

US20160189789A1 Method of Operating a NAND Flash Memory Device 有权
标题翻译：操作NAND闪存器件的方法
公开(公告)号：US20160189789A1
公开(公告)日：2016-06-30
申请号：US15065301
申请日：2016-03-09
申请人： Winbond Electronics Corporation
发明人： Robin John Jigour , Hui Chen , Oron Michael
IPC分类号： G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G06F3/0619 , G06F3/064 , G06F3/0656 , G06F3/0679 , G06F11/1068 , G11C16/20 , G11C16/3404 , G11C29/04 , G11C29/52 , G11C2029/0411
摘要： Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
摘要翻译：可以提供串行NAND闪存，其具有跨页边界连续读取存储器和从逻辑上连续的存储器位置而没有等待间隔的特性，同时还与高性能串行闪存NOR（“HPSF-NOR”）存储器的时钟兼容性读取命令，使得串行NAND闪存可以与为HPSF-NOR存储器设计的控制器一起使用。具有这些兼容性的串行NAND闪存在这里被称为高性能串行闪存NAND（“SPSF-NAND”）存储器。由于使用HPSF-NOR存储器和控制器的器件和系统通常具有极大的空间限制，因此HPSF-NAND还可以提供与引脚数量较少且HPSF-NOR存储器的小封装尺寸相同的物理属性，以实现更高的兼容性。 HPSF-NAND存储器尤其适用于代码阴影应用，即使在更高密度下享受低存储器“NAND存储器阵列”的低“每比特成本”和低每比特功耗。

10. 发明申请

US20160034346A1 NAND Flash Memory Having Internal ECC Processing and Method of Operation Thereof 有权
标题翻译：具有内部ECC处理的NAND闪存及其操作方法
公开(公告)号：US20160034346A1
公开(公告)日：2016-02-04
申请号：US14450188
申请日：2014-08-01
申请人： Winbond Electronics Corporation
发明人： Oron Michael
IPC分类号： G06F11/10 , H03M13/29 , G11C29/52
CPC分类号： G06F11/1068 , G11C16/26 , G11C2029/0411 , H03M13/13 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/27
摘要： A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.
摘要翻译：可以通过使用具有分区数据寄存器和分区缓存寄存器的数据缓冲器，与缓存寄存器相关联的用户可配置内部ECC以及快速坏块管理来实现连续读操作。在数据读取操作期间，ECC状态可由ECC状态位指示。例如，状态（1：1）可能指示连续读取模式，整个数据输出在多页中包含超过4位错误/页面。但是，可能希望知道每个页面或每个页面分区的ECC状态。对于前者，可以在页面输出结束的状态寄存器中确定整个页面的ECC状态。对于后者，可以在输出相应的页面分区之前确定并输出每个页面分区的ECC状态。

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