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1. 发明授权

US09298618B1 Managing cache memory in a parallel processing environment 有权
标题翻译：在并行处理环境中管理高速缓存
公开(公告)号：US09298618B1
公开(公告)日：2016-03-29
申请号：US14154277
申请日：2014-01-14
申请人： Matthew Mattina
发明人： David Wentzlaff , Matthew Mattina , Anant Agarwal
IPC分类号： G06F15/163 , G06F12/08 , G06F12/10
CPC分类号： G06F13/24 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/1027 , G06F12/1045 , G06F13/16 , G06F13/4022 , G06F2212/60 , G06F2212/621 , G06F2212/682 , H04L49/109
摘要： An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
摘要翻译：一种装置包括多个处理器核心，每个处理器核心包括计算单元和存储器。该装置还包括互连网络以在处理器核心之间传送数据。至少一些存储器被配置为处理器核心外部的存储器的高速缓存，并且至少一些处理器核心被配置为通过互连网络传送消息以访问另一处理器核心的高速缓存。

2. 发明授权

US09009660B1 Programming in a multiprocessor environment 有权
标题翻译：在多处理器环境中编程
公开(公告)号：US09009660B1
公开(公告)日：2015-04-14
申请号：US11564723
申请日：2006-11-29
申请人： Patrick Robert Griffin , Walter Lee , Anant Agarwal , David Wentzlaff
发明人： Patrick Robert Griffin , Walter Lee , Anant Agarwal , David Wentzlaff
IPC分类号： G06F9/44 , G06F9/45 , G06F9/48
CPC分类号： G06F8/445 , G06F8/30 , G06F8/314 , G06F8/41 , G06F8/427 , G06F8/437 , G06F8/447 , G06F8/451 , G06F8/453 , G06F9/48 , G06F9/546 , G06F2209/548
摘要： Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.
摘要翻译：在多处理器环境中的编程包括接受定义多个处理模块的程序规范和用于在模块的端口之间发送数据的一个或多个通道，将每个处理模块映射到一组一个或多个处理引擎上互联处理引擎的网络，以及至少一些信道，将网络中的一个或多个处理引擎的一个或多个元素分配给用于在各个处理模块之间发送数据的信道。

3. 发明授权

US08799914B1 Managing shared resource in an operating system by distributing reference to object and setting protection levels 有权
标题翻译：通过分配对象引用和设置保护级别来管理操作系统中的共享资源
公开(公告)号：US08799914B1
公开(公告)日：2014-08-05
申请号：US12885957
申请日：2010-09-20
申请人： Christopher D. Metcalf
发明人： Christopher D. Metcalf
IPC分类号： G06F9/46 , G06F15/76
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Managing processes in a computing system comprising one or more cores includes generating an object in an operating system running on at least one core. A reference to the object is distributed to each of at least one and fewer than all of a plurality of processes to be executed on the at least one core. The operating system controls access to a resource such that processes to which the reference to the object was distributed have access to the resource and processes to which the reference to the object was not distributed do not have access to the resource.
摘要翻译：包括一个或多个核心的计算系统中的管理过程包括在至少一个核上运行的操作系统中生成对象。对对象的引用被分发到要在至少一个核上执行的多个进程中的至少一个且少于全部的进程中的每一个。操作系统控制对资源的访问，使得对对象的引用分配的进程可以访问对对象的引用未分配的资源和进程无权访问该资源。

4. 发明申请

US20140122560A1 High Performance, Scalable Multi Chip Interconnect 有权
标题翻译：高性能，可扩展的多芯片互连
公开(公告)号：US20140122560A1
公开(公告)日：2014-05-01
申请号：US13789801
申请日：2013-03-08
申请人： TILERA CORPORATION
发明人： Carl G. Ramey , Matthew Mattina
IPC分类号： H04L29/08
CPC分类号： G06F15/17312 , H04L49/101 , H04L67/10
摘要： A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.
摘要翻译：描述了一个灵活的，可扩展的服务器。服务器包括多个服务器节点，每个服务器节点包括处理器核心和交换电路，其被配置为将处理器耦合到核心之间的网络，多个核心在计算节点内实现网络功能，其中多个核心网络能力允许核心连接并且向耦合到服务器的网络提供单个接口。

5. 发明授权

US08612711B1 Memory-mapped data transfers 有权
标题翻译：内存映射数据传输
公开(公告)号：US08612711B1
公开(公告)日：2013-12-17
申请号：US12886386
申请日：2010-09-20
申请人： Patrick Robert Griffin
发明人： Patrick Robert Griffin
IPC分类号： G06F12/00
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Receiving data at a first device transferred from a second device includes: storing a starting address with respect to a memory address space for a memory of the first device in a storage location within the first device. A request is received at the first device to transfer one or more data values from the second device, the request including a target address with respect to a communication channel address space for a communication channel between the first device and the second device. The second device determines whether the target address corresponds to a reserved address value designated as an indicator of a transfer to a memory address beyond the communication channel address space. The one or more data values are transferred from the second device to the first device according to the stored starting address if the target address does correspond to the reserved address value, or the one or more data values are transferred from the second device to the first device according to the target address if the target address does not correspond to the reserved address value.
摘要翻译：在从第二设备传送的第一设备处接收数据包括：存储关于第一设备的存储器中的第一设备的存储器的存储器地址空间的起始地址。在第一设备处接收到从第二设备传送一个或多个数据值的请求，该请求包括关于第一设备和第二设备之间的通信信道的通信信道地址空间的目标地址。第二装置确定目标地址是否对应于指定为超出通信信道地址空间的存储器地址的传送的指示符的保留地址值。如果目标地址对应于保留的地址值，则一个或多个数据值根据所存储的起始地址从第二设备传送到第一设备，或者一个或多个数据值从第二设备传送到第一设备如果目标地址不对应于保留地址值，则根据目标地址设备。

6. 发明申请

US20130070588A1 Packet Processing in a Parallel Processing Environment 有权
标题翻译：并行处理环境中的数据包处理
公开(公告)号：US20130070588A1
公开(公告)日：2013-03-21
申请号：US13487361
申请日：2012-06-04
申请人： Kenneth M. Steele , Vijay Aggarwal
发明人： Kenneth M. Steele , Vijay Aggarwal
IPC分类号： H04L12/24 , H04L12/56
CPC分类号： H04L49/90 , H04L47/52 , H04L47/60
摘要： Processing packets in a system that comprises a plurality of interconnected processing cores includes: receiving packets into one or more queues; associating at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate; mapping a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and at least one rate associated with a node not in the set; and processing the packets in the mapped processor cores according to the hierarchy.
摘要翻译：在包括多个互连处理核心的系统中处理分组包括：将分组接收到一个或多个队列中; 将节点层级中的至少一些节点与至少一个队列相关联，并且至少一些节点与速率相关联; 基于集合中的节点的层级中的级别和与不在集合中的节点相关联的至少一个速率将一个或多个节点的集合映射到处理器核心; 并根据层次结构处理映射的处理器核心中的数据包。

7. 发明授权

US08181168B1 Memory access assignment for parallel processing architectures 有权
标题翻译：并行处理架构的内存访问分配
公开(公告)号：US08181168B1
公开(公告)日：2012-05-15
申请号：US12028007
申请日：2008-02-07
申请人： Walter Lee , Robert A. Gottlieb , Vineet Soni , Anant Agarwal , Richard Schooler
发明人： Walter Lee , Robert A. Gottlieb , Vineet Soni , Anant Agarwal , Richard Schooler
IPC分类号： G06F9/445
CPC分类号： G06F8/41 , G06F8/445 , G06F12/0837
摘要： A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; forming one or more memory analysis regions that include one or more of the subsets of instructions, where each subset of instructions is included in a single memory analysis region; analyzing each memory analysis region to partition memory objects and instructions that access the memory objects into equivalence classes such that instructions within an equivalence class only access objects in the same equivalence class; and assigning memory access instructions a given equivalence class to one of the computation units for execution on the assigned computation unit.
摘要翻译：一种系统包括由互连网互连的多个计算单元。一种用于配置系统的方法包括形成与节目的不同部分相对应的指令子集，所述指令子集根据控制流程图相关; 形成包括指令子集中的一个或多个的一个或多个存储器分析区域，其中每个指令子集包括在单个存储器分析区域中; 分析每个存储器分析区域以将存储器对象和将存储器对象访问为等价类的指令分区，使得等价类中的指令仅访问相同等价类中的对象; 以及将存储器访问指令分配给给定的等价类别到所述计算单元之一，以便在所分配的计算单元上执行。

8. 发明授权

US08127111B1 Managing data provided to switches in a parallel processing environment 有权
标题翻译：在并行处理环境中管理提供给交换机的数据
公开(公告)号：US08127111B1
公开(公告)日：2012-02-28
申请号：US12110956
申请日：2008-04-28
申请人： David Wentzlaff , Anant Agarwal
发明人： David Wentzlaff , Anant Agarwal
IPC分类号： G06F15/00
CPC分类号： G06F15/16
摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and coupling circuitry configured to couple data resulting from processing an instruction from at least one of the streams of instructions to the storage module and to the switch.
摘要翻译：集成电路包括多个瓦片。每个瓦片包括包括存储模块的处理器，其中所述处理器被配置为处理多个指令流，开关包括切换电路，以将从其他瓦片到数据路径接收的数据转发到处理器，以及转发其他瓦片从处理器接收的数据到其他瓦片的切换器，以及耦合电路，其被配置为将从指令流中的至少一个处理指令得到的数据耦合到存储模块和交换机。

9. 发明授权

US08112581B1 Caching in multicore and multiprocessor architectures 有权
标题翻译：在多核和多处理器架构中进行缓存
公开(公告)号：US08112581B1
公开(公告)日：2012-02-07
申请号：US12958920
申请日：2010-12-02
申请人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0817
摘要： A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state. Each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.
摘要翻译：多核处理器包括多个高速缓冲存储器; 多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联; 一个或多个存储器接口，提供从高速缓冲存储器到主存储器的存储器访问路径; 以及用于主存储器的相应部分的一个或多个目录控制器，每个与用于目录状态的相应存储器相关联。每个对应的存储器提供用于维护指示为存储在至少一个高速缓存存储器中的每个存储器线的目录状态的空间，使得用于维护目录状态的空间与主存储器的大小无关。

10. 发明授权

US07987321B1 Caching in multicore and multiprocessor architectures 有权
标题翻译：在多核和多处理器架构中进行缓存
公开(公告)号：US07987321B1
公开(公告)日：2011-07-26
申请号：US12966686
申请日：2010-12-13
申请人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0817
摘要： A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
摘要翻译：多核处理器包括多个高速缓存存储器和多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联。至少一些高速缓存存储器中的每一个被配置为保持高速缓冲存储器的至少一部分，其中每个高速缓存行被动态地管理为相关联的处理器核心的本地或在多个处理器核心之间共享。

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