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1. 发明授权

US5136622A Shift register, particularly for a liquid crystal display 失效
标题翻译：移位寄存器，特别是液晶显示器
公开(公告)号：US5136622A
公开(公告)日：1992-08-04
申请号：US660271
申请日：1991-02-28
申请人： Dora Plus
发明人： Dora Plus
IPC分类号： G09G3/36 , G11C19/28
CPC分类号： G09G3/3674 , G11C19/28
摘要： A shift register includes transistors having conduction paths serially connected at a node and between an input terminal receiving a constant voltage and a clocked terminal receiving a clocked voltage of a first phase. The control electrode of one of the transistors receives a clocked voltage of a second phase and the control electrode of the other transistor receives an input signal. An inverter is arranged between the node and the output terminal.
摘要翻译：移位寄存器包括具有在节点处串行连接的导通路径和接收恒定电压的输入端子和接收第一相的时钟控制电压的时钟控制端子之间的晶体管。一个晶体管的控制电极接收第二相的时钟电压，另一个晶体管的控制电极接收输入信号。在节点和输出端之间设置一个逆变器。

2. 发明授权

US5796390A Redundant shift registers for scanning circuits in liquid crystal display devices 失效
标题翻译：冗余移位寄存器用于液晶显示器件中的扫描电路
公开(公告)号：US5796390A
公开(公告)日：1998-08-18
申请号：US37175
申请日：1993-03-24
申请人： Antoine Pierre DuPont , Dora Plus
发明人： Antoine Pierre DuPont , Dora Plus
IPC分类号： G06F11/00 , G09G3/36 , G11C19/00 , G11C19/28 , G11C29/00 , H04N5/66
CPC分类号： G11C29/86 , G09G3/3677 , G09G2330/08
摘要： A display device having a plurality of select lines includes redundant select line scanners. Each scanner includes a plurality of substantially identical stages having an input terminal and an output terminal. The stages and select lines are ordinally numbered and correspondingly numbered stages are connected to opposite ends of the correspondingly numbered select lines by separate line segments. The stages within each scanner are cascaded by connecting the output terminal of each stage to the input terminal of the immediately succeeding stage. Failed stages of a scanner are replaced by the correspondingly numbered stage of the other scanner simply by opening the separate line segment of the failed stage.
摘要翻译：具有多条选择线的显示装置包括冗余选择线扫描器。每个扫描器包括具有输入端和输出端的多个基本相同的级。阶段和选择线被顺序编号，并且相应编号的级通过单独的线段连接到对应编号的选择线的相对端。通过将每个级的输出端子连接到紧随其后的级的输入端子，级联各个扫描器。扫描仪的失败阶段只需打开失败阶段的单独线段即可用其他扫描仪的相应编号的级替代。

3. 发明授权

US5195010A Electrostatic discharge voltage protection circuit for a solid state instrument 失效
标题翻译：静电放电电压保护电路用于固态仪器
公开(公告)号：US5195010A
公开(公告)日：1993-03-16
申请号：US468510
申请日：1990-01-23
申请人： Joseph Dresner
发明人： Joseph Dresner
IPC分类号： H01L27/02 , H02H9/04
CPC分类号： H01L27/0248 , H02H9/046
摘要： A protection circuit for a solid state instrument includes a plurality of fuses and a switching device arranged in parallel with the input capacitance of the solid state instrument, The fuses protect the instrument from high voltage surges, and the switching device protects the instrument from lower voltage surges. The fuses and the switching device are solid state devices and thus can be fabricated along with the solid state instrument.
摘要翻译：用于固态器件的保护电路包括多个保险丝和与固态器件的输入电容并联布置的开关器件。保险丝保护器件免受高压浪涌，并且开关器件保护器件免受较低的电压激增保险丝和开关装置是固态器件，因此可以与固态器件一起制造。

4. 发明授权

US5175446A Demultiplexer including a three-state gate 失效
标题翻译：分解器包括三态门
公开(公告)号：US5175446A
公开(公告)日：1992-12-29
申请号：US655498
申请日：1991-02-14
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G09G3/20 , G09G3/36 , H03K17/693 , H03M7/22
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/027
摘要： A demultiplexer includes a plurality of transistors having conduction paths connected between an input terminal and output nodes. The control electrode of every transistor is connected to one line of a most significant bit bus by a first capacitive device, the control electrode of every transistor is also coupled to one line of a least significant bit bus by a second capacitive device. When the capacitive devices associated with the same transistor simultaneously receive an enable signal the transistor is turned on and current flows from the input terminal to an output node. Each transistor within the demultiplexer thus acts as a three state gate.
摘要翻译：解复用器包括具有连接在输入端和输出节点之间的导通路径的多个晶体管。每个晶体管的控制电极通过第一电容器件连接到最高有效位总线的一行，每个晶体管的控制电极也通过第二电容器件耦合到最低有效位总线的一行。当与同一晶体管相关联的电容器件同时接收使能信号时，晶体管导通，电流从输入端流向输出节点。因此，解多路器中的每个晶体管用作三态门。

5. 发明授权

US5093581A Circuitry for generating pulses of variable widths from binary input data 失效
标题翻译：用于从二进制输入数据产生可变宽度的脉冲的电路
公开(公告)号：US5093581A
公开(公告)日：1992-03-03
申请号：US620684
申请日：1990-12-03
申请人： George R. Briggs , Roger G. Stewart
发明人： George R. Briggs , Roger G. Stewart
IPC分类号： G09G3/36 , G09G3/20 , H03K5/00 , H03K5/13 , H03K5/135 , H03K7/08 , H03M1/82
CPC分类号： H03K7/08 , H03K5/131 , H03K5/135 , H03K2005/00195
摘要： A variable width pulse generator includes a plurality of logic stages which are coupled in cascade. Each stage is arranged to select one of a plurality of clock signals of differing phase applied thereto responsive to particular bits of a data word defining the pulse width. All of the stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are enabled by the occurrence of a clock pulse of a clock signal selected by the previous stage. The lastmost stage provides an output corresponding to the variable width pulse.
摘要翻译：可变宽度脉冲发生器包括级联耦合的多个逻辑级。每个级被布置成响应于定义脉冲宽度的数据字的特定位来选择施加到其上的不同相位的多个时钟信号中的一个。所有阶段最初由在每个可变脉冲间隔开始时发生的预充电脉冲而被禁用。通过出现由前一级选择的时钟信号的时钟脉冲使连续级能够实现。最后一个阶段提供对应于可变宽度脉冲的输出。

6. 发明授权

US5170155A System for applying brightness signals to a display device and comparator therefore 失效
标题翻译：用于将亮度信号应用于显示设备的系统以及由此产生的比较器
公开(公告)号：US5170155A
公开(公告)日：1992-12-08
申请号：US600046
申请日：1990-10-19
申请人： Dora Plus , Leopold A. Harwood
发明人： Dora Plus , Leopold A. Harwood
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/0259 , G09G2310/027
摘要： A system for applying brightness signals to the pixels of a display device includes a transmission gate for each column of pixels. The control electrodes of the transmission gates are precharged to the threshold voltage of the gates to substantially increase the speed of the system. Comparators compare brightness voltages to a reference ramp voltage to enhance the speed and accuracy of the system.
摘要翻译：用于将亮度信号施加到显示装置的像素的系统包括用于每列像素的传输门。传输门的控制电极被预充电到门的阈值电压，以显着提高系统的速度。比较器将亮度电压与参考斜坡电压进行比较，以提高系统的速度和精度。

7. 发明授权

US5148058A Logic circuits as for amorphous silicon self-scanned matrix arrays 失效
标题翻译：用于非晶硅自扫描矩阵阵列的逻辑电路
公开(公告)号：US5148058A
公开(公告)日：1992-09-15
申请号：US620682
申请日：1990-12-03
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G02F1/133 , G02F1/136 , G02F1/1368 , G09G3/20 , G09G3/36
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/027
摘要： A logic circuit includes pull-up and pull-down transistors and a capacitance, the principal conducting paths of the transistors and the capacitance being coupled in series between a first supply bus and a source of time varying potential. The pull-up transistor is coupled to the capacitance and the capacitance is coupled to the time varying potential. First and second logic signals are applied to the control electrodes of the first and second transistors respectively. The time varying potential is arranged to limit the charge passed by the pull-up transistor permitting use of a relatively small pull-down transistor. The time varying potential has an amplitude sufficiently large to tend to stress the pull-up transistor if such transistor is non conducting. A selectively conductive element (diode) is coupled between a point of clamping potential and the interconnection of the pull-up transistor and capacitance.
摘要翻译：逻辑电路包括上拉和下拉晶体管和一个电容，晶体管的主要导电路径和电容串联在第一电源总线和时变电源之间。上拉晶体管耦合到电容，并且电容耦合到时变电位。第一和第二逻辑信号分别施加到第一和第二晶体管的控制电极。时变电位被布置为限制允许使用相对较小的下拉晶体管的上拉晶体通过的电荷。如果这种晶体管不导通，则时变电位具有足够大的幅度以倾向于对上拉晶体管施加应力。选择性导电元件（二极管）耦合在钳位电位点和上拉晶体管与电容互连之间。

8. 发明授权

US5113134A Integrated test circuit for display devices such as LCD's 失效
标题翻译： LCD等显示设备的集成测试电路
公开(公告)号：US5113134A
公开(公告)日：1992-05-12
申请号：US660275
申请日：1991-02-28
申请人： Dora Plus , Bruno B. Mourey
发明人： Dora Plus , Bruno B. Mourey
IPC分类号： G01R31/28 , G01R31/00 , G01R31/02 , G09G3/00 , G09G3/36
CPC分类号： G09G3/006 , G01R31/024 , G09G2330/12 , G09G3/3648 , Y10S345/904
摘要： A circuit for testing a liquid crystal display for open data lines, for identifying select lines shorted to data lines, and for identifying failed data line scanner stages includes thin film transistors arranged between each data line and a segmented bus. A sectioned shift register sequentially actuates the thin film transistors and the bus segments are monitored while data signals are applied to the data lines. The absence of a voltage on the bus indicates an open data line. The bus is also monitored while select signals are applied to the select lines and the shift register sequentially actuates the thin film transistors, the presence of a voltage on the bus indicates a short between a data line and a select line.
摘要翻译：用于测试用于开放数据线的液晶显示器的电路，用于识别短路到数据线的选择线，以及用于识别故障数据线扫描器级的电路包括布置在每个数据线和分段总线之间的薄膜晶体管。分段移位寄存器顺序地致动薄膜晶体管，并且在将数据信号施加到数据线的同时监视总线段。总线上没有电压表示打开的数据线。当选择信号被施加到选择线并且移位寄存器顺序地驱动薄膜晶体管时，总线也被监视，总线上的电压的存在指示数据线和选择线之间的短路。

9. 发明授权

US5103112A Apparatus for generating control pulses of variable width, as for driving display devices 失效
标题翻译：用于产生可变宽度的控制脉冲的装置，用于驱动显示装置
公开(公告)号：US5103112A
公开(公告)日：1992-04-07
申请号：US620683
申请日：1990-12-03
申请人： George R. Briggs
发明人： George R. Briggs
IPC分类号： G09G3/36 , G06F1/025 , H03K5/04 , H03M1/82
CPC分类号： G06F1/025 , H03K5/04
摘要： A variable width pulse generator includes a plurality of logic stages which are coupled cascade. Each stage is arranged to select one of a plurality of clock signals of differing phase applied thereto responsive to particular bits of a data word defining the pulse width. All of the stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are enabled by the occurrence of a clock pulse of a clock signal selected by the previous stage. The lastmost stage provides an output corresponding to the width pulse.
摘要翻译：可变宽度脉冲发生器包括耦合级联的多个逻辑级。每个级被布置成响应于定义脉冲宽度的数据字的特定位来选择施加到其上的不同相位的多个时钟信号中的一个。所有阶段最初由在每个可变脉冲间隔开始时发生的预充电脉冲而被禁用。通过出现由前一级选择的时钟信号的时钟脉冲使连续级能够实现。最后一级提供对应于宽度脉冲的输出。

10. 发明授权

US5122676A Variable pulse width generator including a timer vernier 失效
标题翻译：可变脉冲宽度发生器，包括定时器VERNIER
公开(公告)号：US5122676A
公开(公告)日：1992-06-16
申请号：US620681
申请日：1990-12-03
申请人： Roger G. Stewart , George R. Briggs
发明人： Roger G. Stewart , George R. Briggs
IPC分类号： G09G3/20 , G09G3/36 , H03M1/82
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/0259 , G09G2310/027
摘要： A pulse logic circuit comprises a plurality of interconnected stages. Each of the stages includes a relatively large node-charging transistor which, when enabled, forwards charging current to a node from a timing pulse of one of a plurality of phases applied to a load capacitance in series with the node-charging transistor. Such large transistors exhibit significant gate-to-source and gate-to drain distributed capacitances. The response time for charging a selected stage node can be decreased by precharging the gate of the node-charging transistor of a selected stage to enable the transistor prior to the application of a timing pulse, thereby increasing the maximum operating speed of the circuit. Disclosed species of such a pulse logic circuit include time vernier circuits which can be utilized as control circuitry for a liquid crystal television or computer display.
摘要翻译：脉冲逻辑电路包括多个互连级。每个级包括相对较大的节点充电晶体管，其在使能时，从施加到与节点充电晶体管串联的负载电容的多个相中的一个相的定时脉冲向节点转发充电电流。这种大型晶体管表现出显着的栅极到源极和栅极到漏极分布电容。通过对选定级的节点充电晶体管的栅极进行预充电，可以在施加定时脉冲之前使晶体管使能，从而提高电路的最大工作速度，可以减小对选定级节点充电的响应时间。这种脉冲逻辑电路的公开物种包括可用作液晶电视或计算机显示器的控制电路的时间游标电路。

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